Electrically conductive interconnect including via having increased contact surface area

Patent metadata

Field	Value
Publication number	US-9553044-B2
Application number	US-201414533636-A
Country	US
Kind code	B2
Filing date	Nov 5, 2014
Priority date	Nov 5, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.

First claim

What is claimed is:

1. A method of fabricating an interconnect structure, the method comprising:
forming a multilayer dielectric layer extending along a first axis to define a height and a second axis opposite the first axis to define a length, the multiple dielectric layers including a capping layer interposed between a first dielectric layer and a second dielectric layer, at least one of the first and second dielectric layer including at least one electrically conductive feature embedded therein;
etching the second dielectric layer to form an opening that extends parallel with respect to the first axis, and performing an isotropic etching process to etch the capping layer and form a trench having a curved-shape that extends along the second axis and substantially perpendicular with respect to the first axis so as to undercut the capping layer, the isotropic etching process defining at least one cavity beneath the second dielectric layer that defines a void between the second dielectric layer and the capping layer; and
depositing an electrically conductive material in the opening, the trench, and the at least one cavity to form an electrically conductive via including a narrow via portion and a flange, the narrow via portion extending parallel with the respect first axis, the flange having at least one portion extending laterally away from the via along the second axis to define a contact area between the via and the at least one conductive feature, the contact area extending substantially perpendicular to the first axis and being located completely beneath the second dielectric layer, the contact area of the flange having a curve-shaped lower portion that directly contacts the at least one electrically conductive feature and having a width extending along the second axis that is greater than a width of the narrow via portion extending along the second axis.

2. The method of claim 1 , wherein the etching comprises:
performing a first etching process that stops on the capping layer such that the opening extends from an upper surface of the second dielectric layer to the capping layer;
performing a second etching process that etches the capping layer and stops on an upper surface of the at least one conductive feature to form a trench in the capping layer.

3. The method of claim 2 , further comprising etching the trench beyond the second dielectric layer such that at least one cavity is located beneath the second dielectric layer.

4. The method of claim 3 , wherein the trench is interposed between the first dielectric layer and the second dielectric layer.

5. The method of claim 4 , further comprising forming the trench in only the capping layer such that contact flange is formed in only the capping area without extending through the at least one conductive feature.

6. The method of claim 5 , wherein the contact area is formed in the capping layer without extending into the at least one conductive feature.

7. The method of claim 6 , further comprising disposing a portion of the contact flange against the second dielectric layer.

8. The method of claim 7 , further comprising forming a conformal metal film layer on the via, the metal film layer configured to inhibit metal ions from diffusing into the first dielectric layer, the second dielectric layer and the capping layer.

9. The method of claim 8 , wherein the via and the at least one conductive feature comprise a metal material.

10. The method of claim 9 , wherein the capping layer comprises a dielectric material, and wherein the first and second dielectric layers comprises a low-k dielectric material different from the first dielectric material of the capping layer.

Assignees

• IBM

Inventors

• Chen Hsueh-Chung
• Demarest James J
• Teehan Sean
• Yang Chih-Chao

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title