Silicon carbide switching devices including P-type channels

Patent metadata

Field	Value
Publication number	US-9552997-B2
Application number	US-201113019723-A
Country	US
Kind code	B2
Filing date	Feb 2, 2011
Priority date	Jun 29, 2006
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is in the channel region and includes p-type dopants at a dopant concentration of about 1×10 16 cm −3 to about 5×10 18 cm −3 . The transistor further includes a gate oxide layer on the channel region, and a gate on the gate oxide layer. The transistor may exhibit a hole mobility in the channel region in excess of 5 cm 2 /V-s at a gate voltage of −25V.

First claim

What is claimed is:

1. A silicon carbide-based transistor, comprising:
a silicon carbide layer;
an n-type well in the silicon carbide layer;
a p-type region in the n-type well at a surface of the silicon carbide layer, the p-type region defining at least partially a first region in the n-type well adjacent the p-type region;
a threshold adjustment layer on the first region, the threshold adjustment layer comprising an n-type epitaxial layer on the n-type well;
an implanted channel in the threshold adjustment layer, the implanted channel comprising p-type dopants at a dopant concentration of about 1×10 16 cm −3 to about 5×10 18 cm −3 , wherein the implanted channel is positioned at a distance from a surface of the threshold adjustment layer;
a gate oxide layer on a surface of the channel region; and
a gate on the gate oxide layer;
wherein the implanted channel has a hole mobility of at least about 5 cm 2 /V-s at a gate voltage of −25V.

2. The transistor of claim 1 , wherein the silicon carbide layer comprises an n-type silicon carbide layer, and wherein the p-type region comprises a p-type source region, the transistor further comprising a p-type drain region spaced apart from the p-type source region and defining the first region between the p-type source region and the p-type drain region.

3. The transistor of claim 1 , wherein the silicon carbide layer comprises a p-type silicon carbide layer including a JFET region adjacent to the n-type well, and wherein the p-type region comprises a p-type emitter region spaced apart from the JFET region and defining the first region between the p-type emitter region and the JFET region.

4. The transistor of claim 1 , wherein the threshold adjustment layer has a thickness of about 100 nm to about 300 nm.

5. The transistor of claim 1 , wherein the implanted channel has a hole mobility of at least about 10 cm 2 /V-s at a gate voltage of −25V.

6. The transistor of claim 1 , wherein the implanted channel has a hole mobility of at least about 13 cm 2 /V-s at a gate voltage of −20V.

7. A silicon carbide-based transistor, comprising:
an n-type silicon carbide layer;
a p-type silicon carbide layer on the n-type silicon carbide layer;
an n-type well in the p-type silicon carbide layer;
a p-type region in the n-type well at a surface of the silicon carbide layer, the p-type region defining at least partially a first region in the n-type well adjacent the p-type region;
a threshold adjustment layer on the first region, the threshold adjustment layer comprising an n-type epitaxial layer on the n-type well;
an implanted channel in the threshold adjustment layer, the implanted channel comprising p-type dopants at a dopant concentration of about 1×10 16 cm −3 to about 5×10 18 cm −3 , wherein the implanted channel is positioned at a distance from a surface of the threshold adjustment layer;
a gate oxide layer on the channel region; and
a gate on the gate oxide layer;
wherein the implanted channel region has a hole mobility of at least about 5 cm 2 /V-s at a gate voltage of −25V.

8. The transistor of claim 7 , wherein the p-type silicon carbide layer includes JFET region adjacent to the n-type well, and wherein the p-type region comprises a p-type emitter region spaced apart from the WET region and defining the first region between the p-type emitter region and the JFET region.

9. The transistor of claim 7 , wherein the threshold adjustment layer has a thickness of about 100 nm to about 500 nm.

10. The transistor of claim 7 , wherein the implanted channel has a hole mobility of at feast about 10 cm 2 /V-s at a gate voltage of −25V.

11. The transistor of claim 7 , wherein the implanted channel has a hole mobility of at least about 13 cm 2 /V-s at a gate voltage of −20V.

Assignees

• Das Mrinal Kanti
• Zhang Qingchun
• Ryu Sei-Hyung
• Cree Inc

Inventors

• Das Mrinal Kanti
• Zhang Qingchun
• Ryu Sei-Hyung

Classifications

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/01366

  the semiconductor being silicon carbide · CPC title

• H10P95/90 Primary

  Thermal treatments, e.g. annealing or sintering · CPC title

• Y10S438/931

  Silicon carbide semiconductor · CPC title