Solid-state electrolytic capacitor manufacturing method and solid-state electrolytic capacitor

US9552928B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9552928-B2
Application numberUS-201314049320-A
CountryUS
Kind codeB2
Filing dateOct 9, 2013
Priority dateApr 20, 2011
Publication dateJan 24, 2017
Grant dateJan 24, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A solid electrolytic capacitor having grooves provided in a valve-acting metal substrate that includes a porous surface part and a non-porous body part, the bottoms of the grooves being non-porous. The valve-acting metal substrate is divided into a plurality of unit regions by the grooves, and define cathode layer formation parts in the porous surface parts for each unit region. A dielectric layer covers the surfaces of the cathode layer formation parts of the valve-acting metal substrate and the grooves between the cathode layer formation parts. A solid electrolyte layer and a cathode extraction layer cover the surface of the dielectric layer, thereby providing a sheet in which a plurality of solid electrolytic capacitor elements are prepared integrally with the grooves interposed therebetween. The sheet is cut at the grooves, and a dielectric layer is formed on the cut surfaces located around the cathode layer formation parts.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing a solid electrolytic capacitor, the method comprising: (a) forming grooves in opposed principal surfaces of a valve-acting metal substrate that includes a porous surface part and a non-porous body part such that bottoms of the grooves are non-porous, partitioning the opposed principal surfaces of the valve-acting metal substrate into a plurality of unit regions at the grooves, and defining a cathode layer formation part in the porous surface part for each unit region; (b) forming a first dielectric layer on surfaces of the cathode layer formation parts of the valve-acting metal substrate and on the grooves between the cathode layer formation parts; (c) sequentially forming a solid electrolyte layer and a cathode extraction layer on a surface of the first dielectric layer formed on the cathode layer formation parts of the valve-acting metal substrate so as to provide a sheet having a plurality of solid electrolytic capacitor elements corresponding to the plurality of unit regions integral with the grooves interposed therebetween; (d) cutting the sheet at the grooves of the valve-acting metal substrate; and (e) forming a second dielectric layer on cut surfaces located around the cathode layer formation parts of the valve-acting metal substrate. 2. The method for manufacturing a solid electrolytic capacitor according to claim 1 , wherein steps (a) to (c) are applied to each of a plurality of the valve-acting metal substrates to form a plurality of sheets, stacking the plurality of sheets, and cutting at the grooves of the valve-acting metal substrates of the plurality of sheets. 3. The method for manufacturing a solid electrolytic capacitor according to claim 1 , wherein the grooves of the valve-acting metal substrate are formed by pressing the valve-acting metal substrate in a thickness direction. 4. The method for manufacturing a solid electrolytic capacitor according to claim 1 , wherein the grooves of the valve-acting metal substrate are formed by removing the porous surface part from the valve-acting metal substrate. 5. A method for manufacturing a solid electrolytic capacitor, the method comprising: (a) forming grooves in opposed principal surfaces of a valve-acting metal substrate that includes a porous surface part and a non-porous body part such that bottoms of the grooves are non-porous, partitioning the opposed principal surfaces of the valve-acting metal substrate into a plurality of unit regions at the grooves, and defining a cathode layer formation part in the porous surface part for each unit region; (b) forming a resist layer on the bottoms of the grooves, and forming a dielectric layer on the surfaces of the cathode layer formation parts of the valve-acting metal substrate is carried out; (c) sequentially forming a solid electrolyte layer and a cathode extraction layer on a surface of the first dielectric layer formed on the cathode layer formation parts of the valve-acting metal substrate so as to provide a sheet having a plurality of solid electrolytic capacitor elements corresponding to the plurality of unit regions integral with the grooves interposed therebetween; (d) cutting the sheet at the grooves of the valve-acting metal substrate; and (e) forming a second dielectric layer on cut surfaces located around the cathode layer formation parts of the valve-acting metal substrate. 6. The method for manufacturing a solid electrolytic capacitor according to claim 5 , wherein steps (a) to (c) are applied to each of a plurality of the valve-acting metal substrates to form a plurality of sheets, stacking the plurality of sheets, and cutting at the grooves of the valve-acting metal substrates of the plurality of sheets. 7. A method for manufacturing a solid electrolytic capacitor, the method comprising: (a) forming grooves in opposed principal surfaces of a plurality of valve-acting metal substrate that includes a porous surface part and a non-porous body part such that bottoms of the grooves are non-porous, partitioning the opposed principal surfaces of the plurality of valve-acting metal substrate into a plurality of unit regions at the grooves, and defining a cathode layer formation part in the porous surface part for each unit region; (b) forming a first dielectric layer on surfaces of the cathode layer formation parts of the plurality of valve-acting metal substrates and on the grooves between the cathode layer formation parts; (c) stacking the plurality of valve-acting metal substrates with to form a laminate; (d) joining adjacent valve-acting metal substrates in the laminate to each other to obtain a joined laminate; (e) forming a continuous solid electrolyte layer so as to fill gaps between the first dielectric layers formed on surfaces of cathode layer formation parts of adjacent valve-acting metal substrates in the joined laminate, and coating an outer surface of the joined laminate in the cathode layer formation parts; (f) cutting the joined laminate at the grooves of the plurality of valve-acting metal substrates; and (g) forming a second dielectric layer on cut surfaces located around the cathode layer formation parts of the plurality of valve-acting metal substrates. 8. The method for manufacturing a solid electrolytic capacitor according to claim 7 , wherein the grooves of the plurality of valve-acting metal substrate are formed by pressing the plurality of valve-acting metal substrates in a thickness direction. 9. The method for manufacturing a solid electrolytic capacitor according to claim 7 , wherein the grooves of the valve-acting metal substrate are formed by removing the porous surface part from the plurality of valve-acting metal substrates. 10. A method for manufacturing a solid electrolytic capacitor, the method comprising: (a) forming grooves in opposed principal surfaces of a plurality of valve-acting metal substrate that includes a porous surface part and a non-porous body part such that bottoms of the grooves are non-porous, partitioning the opposed principal surfaces of the plurality of valve-acting metal substrate into a plurality of unit regions at the grooves, and defining a cathode layer formation part in the porous surface part for each unit region; (b) forming a resist layer on the bottoms of the grooves, and forming a dielectric layer on the surfaces of the cathode layer formation parts of the valve-acting metal substrate is carried out; (c) stacking the plurality of valve-acting metal substrates with to form a laminate; (d) joining adjacent valve-acting metal substrates in the laminate to each other to obtain a joined laminate; (e) forming a continuous solid electrolyte layer so as to fill gaps between the first dielectric layers formed on surfaces of cathode layer formation parts of adjacent valve-acting metal substrates in the joined laminate, and coating an outer surface of the joined laminate in the cathode layer formation parts; (f) cutting the joined laminate at the grooves of the plurality of valve-acting metal substrates; and (g) forming a second dielectric layer on cut surfaces located around the cathode layer formation parts of the plurality of valve-acting metal substrates.

Assignees

Inventors

Classifications

  • H01G9/0032Primary

    formation of the dielectric layer · CPC title

  • Solid electrolytes (H01G11/54 takes precedence) · CPC title

  • H01G9/15Primary

    Solid electrolytic capacitors (H01G11/00 takes precedence) · CPC title

  • Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00 · CPC title

  • Etched foil electrodes · CPC title

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What does patent US9552928B2 cover?
A solid electrolytic capacitor having grooves provided in a valve-acting metal substrate that includes a porous surface part and a non-porous body part, the bottoms of the grooves being non-porous. The valve-acting metal substrate is divided into a plurality of unit regions by the grooves, and define cathode layer formation parts in the porous surface parts for each unit region. A dielectric la…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G9/0032. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).