Magnetic ram array architecture

Patent metadata

Field	Value
Publication number	US-9552862-B2
Application number	US-201514812812-A
Country	US
Kind code	B2
Filing date	Jul 29, 2015
Priority date	Jul 29, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron.

First claim

The invention claimed is:

1. A magnetic random access memory (MRAM) array comprising:
a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element;
a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines comprising of a memory word; and
a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the MRAM array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron.

2. The MRAM array of claim 1 , wherein the magnetic memory element is a Cryogenic Orthogonal Spin-Transfer (COST) device.

3. The MRAM array of claim 2 , wherein the each of the plurality of MRAM cells further comprises of an inductance.

4. The MRAM array of claim 1 , wherein the magnetic memory element is a Cryogenic Spin Hall Effect (CSHE) device.

5. The MRAM array of claim 1 , wherein the second type nTron is capable of driving a linear array of 64 first type nTrons for a memory word of 64 bits wide.

6. The MRAM array of claim 1 , further comprising a Single Flux Quantum (SFQ) comparator for reading a state of each MRAM cell, during the memory read operation.

7. The MRAM array of claim 6 , wherein the SFQ comparator senses a resistance of said each MRAM cell for reading the state of said each MRAM cell.

8. The MRAM array of claim 1 , wherein during a memory read operation, the second type nTron applies a current to the memory element smaller than a critical current of the memory element to keep the memory element at its current state while being read.

Assignees

• Raytheon Bbn Technologies Corp
• Hypres Inc

Inventors

• Ohki Thomas
• Mukhanov Oleg
• Kirichenko Alex

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title