Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US9552765B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9552765-B2 |
| Application number | US-201414272653-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 8, 2014 |
| Priority date | Aug 13, 2013 |
| Publication date | Jan 24, 2017 |
| Grant date | Jan 24, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A pixel includes a switching transistor connected to a data line, a first circuit to control compensation of a first driving transistor, and a second circuit to control compensation of a second driving transistor. The first and second circuits are connected to the switching transistor. The first and second transistors are connected to respective organic light emitting diodes of a same pixel. Compensation of the first and second driving transistors is based on respective first and second subscan signals, which overlap periods of corresponding common scan signals to be received by the switching transistor.
Opening claim text (preview).
What is claimed is: 1. A pixel comprising: a switching transistor including a terminal connected to a data line, the switching transistor to perform a switching operation based on a first common scan signal; a first compensation transistor to perform a switching operation based on a first sub scan signal; a second compensation transistor to perform a switching operation based on a second sub scan signal; a first driving transistor including a source connected to another terminal of the switching transistor, the first driving transistor to control a first driving current based on a first data signal transmitted when the first compensation transistor and the switching transistor are turned on; a second driving transistor including a source connected to the other terminal of the switching transistor, the second driving transistor to control a second driving current based on a second data signal transmitted when the second compensation transistor and the switching transistor are turned on; a first light emitting device figured to emit light based on the first driving current; and a second light emitting device to emit light based on the second driving current, wherein: the first common scan signal includes two enable pulses during one frame period, an enable pulse of the first sub scan signal overlaps one of the two enable pulses of the first common scan signal, and an enable pulse of the second sub scan signal overlaps the other one of the two enable pulses of the first common scan signal. 2. The pixel as claimed in claim 1 , further comprising: a first capacitor connected between a gate of the first driving transistor and a first power source voltage; and a second capacitor connected between a gate of the second driving transistor and the first power source voltage. 3. The pixel as claimed in claim 2 , further comprising: a first initialization transistor configured to transmit an initialization voltage to a first node connected to the gate of the first driving transistor and the first capacitor according to a second common scan signal; and a second initialization transistor configured to transmit the initialization voltage to a second node connected to the gate of the second driving transistor and the second capacitor according to the second common scan signal. 4. The pixel as claimed in claim 3 , wherein: each of the first common scan signal and the second common scan signal includes two enable pulses, and the two enable pulses of the first common scan signal are before the two enable pulses of the second common scan signal. 5. The pixel as claimed in claim 1 , wherein: the first compensation transistor is connected between a gate and a drain of the first driving transistor, and the second compensation transistor is connected between a gate and a drain of the second driving transistor. 6. The pixel as claimed in claim 1 , further comprising: a first light emission transistor connected to sources of the first driving transistor and the second driving transistor and to a first power source voltage, wherein the first light emission transistor is turned on after the first data signal and the second data signal are written in gates of the first and second driving transistors, respectively. 7. The pixel as claimed in claim 1 , further comprising: a second light emission transistor connected between a drain of the first driving transistor and the first light emitting device; and a third light emission transistor connected between a drain of the second driving transistor and the second light emitting device, wherein the second and third light emission transistors are turned on after the first data signal and the second data signal are written in gates of the first and second driving transistors, respectively. 8. A method of driving a pixel, the method comprising: turning on a switching transistor based on one of two enable pulses of a first common scan signal; turning on a first compensation transistor based on a first sub scan signal; transmitting a first data signal to a gate of a first driving transistor through the turned on switching transistor and first compensation transistor; turning on the switching transistor based on the other one of the two enable pulses of the first common scan signal; turning on a second compensation transistor based on a second sub scan signal; and transmitting a second data signal to a gate of a second driving transistor through the turned on switching transistor and second compensation transistor, wherein a turn-on period of the switching transistor overlaps turn-on periods of the first and second compensation transistors and wherein the turn-on periods of the first and second compensation transistors are at different times. 9. The method as claimed in claim 8 , further comprising: maintaining a voltage transmitted to the gate of the first driving transistor by a first capacitor based on the first data signal; and maintaining a voltage transmitted to the gate of the second driving transistor by a second capacitor based on the second data signal. 10. The method as claimed in claim 9 , further comprising: transmitting an initialization voltage to a first node connected to the gate of the first driving transistor and the first capacitor according to a second common scan signal; and transmitting the initialization voltage to a second node connected to the gate of the second driving transistor and the second capacitor according to the second common scan signal. 11. The method as claimed in claim 10 , wherein transmitting the initialization voltage to the first node and the second node is performed before the switching transistor, the first compensation transistor, and the second compensation transistor are turned on. 12. The method as claimed in claim 8 , wherein, after the first data signal and the second data signal are written in the gates of the first and second driving transistors, respectively, the method includes: controlling a first driving current to flow through the first driving transistor to cause a first light emitting device to emit light; and controlling a second driving current to flow through the second driving transistor to cause a second light emitting device to emit light. 13. A display device, comprising: a plurality of common scan lines, a plurality of first sub scan lines, a plurality of second sub scan lines, a plurality of light emission control lines, and a plurality of data lines; and a plurality of pixels, each pixel is connected to two corresponding common scan lines, a corresponding one of the first sub scan lines, a corresponding one of the second sub scan lines, a corresponding one of the light emission control lines, and a corresponding one of the data lines, and wherein each pixel includes: a first light emitting device and a second light emitting device; a switching transistor including a first terminal connected to the corresponding data line and a gate connected to a first one of the two common scan lines; a first driving transistor including a source connected to a second terminal of the switching transistor, the first driving transistor configured to control a first driving current supplied to the first light emitting device; a second driving transistor including a source connected to the second terminal of the switching transistor, the second driving transistor configured to control a second driving current supplied to the second light emitting device; a first compensation transistor connected between a gate and a drain of the first driving transistor, the first compensation transistor including a gate connected to the corresponding first sub
with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title
Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements · CPC title
being a dynamic memory with more than one capacitor · CPC title
with pixel circuitry controlling the current through the light-emitting element · CPC title
used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.