Camera control interface extension bus

Patent metadata

Field	Value
Publication number	US-9552325-B2
Application number	US-201414302362-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Jun 12, 2013
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

First claim

What is claimed is:

1. A method of data communication comprising:
generating, at a first device, a transition number from a set of bits;
converting, at the first device, the transition number into a sequence of symbols, wherein timing information is encoded in transitions between symbols in the sequence of symbols; and
transmitting, from the first device, the sequence of symbols on a two-wire serial bus when the two-wire serial bus is operated in a first mode of operation, wherein each transition between consecutive symbols causes a change in a signaling state of the two-wire serial bus,
wherein, while the two-wire serial bus is in the first mode of operation, the sequence of symbols is ignored by a second device coupled to the two-wire serial bus, and
wherein the second device is configured for communicating on the two-wire serial bus using a second mode of operation of the two-wire serial bus.

2. The method of claim 1 , wherein the transition number comprises a twelve digit ternary number.

3. The method of claim 1 , wherein converting the transition number into the sequence of symbols comprises:
converting the set of bits to a ternary transition number; and
providing the ternary transition number to a transcoder, wherein a most significant digit of the ternary transition number is provided to the transcoder first, a least significant digit of the ternary transition number is provided to the transcoder last, and intermediate digits between the most significant digit and the least significant digit are provided to the transcoder in order of decreasing significance.

4. The method of claim 1 , wherein converting the transition number into the sequence of symbols comprises:
converting the set of bits to a ternary transition number; and
providing the ternary transition number to a transcoder, wherein a most significant digit of the ternary transition number is provided to the transcoder last.

5. The method of claim 1 , wherein four signaling states are defined for the two-wire serial bus, and wherein each digit of the transition number selects a next symbol to be transmitted on the two-wire serial bus from one of three available symbols, each of the three available symbols being different from a current symbol being transmitted on the two-wire serial bus.

6. The method of claim 1 , wherein timing information encoded in the sequence of symbols enables a receiver to generate a receive clock from the sequence of symbols.

7. The method of claim 1 , wherein the two-wire serial bus is a multi-purpose bus that supports communications using camera control interface extension (CCIe) protocols when the two-wire serial bus is operated in the first mode of operation, and wherein the two-wire serial bus supports communications using Inter-Integrated Circuit (I2C) protocols in the second mode of operation.

8. The method of claim 7 , wherein transmitting the sequence of symbols on the two-wire serial bus comprises:
providing an I2C start condition between sequences of symbols transmitted on the two-wire serial bus in the first mode of operation,
wherein timing of the start condition causes a reset of receive logic in a device configured for communications using the I2C protocols.

9. The method of claim 7 , wherein transmitting the sequence of symbols on the two-wire serial bus comprises:
transmitting a first I2C start condition on the two-wire serial bus;
transmitting the sequence of symbols on the two-wire serial bus after the first I2C start condition is transmitted; and
transmitting a second I2C start condition on the two-wire serial bus,
wherein an I2C receiver monitoring the two-wire serial bus perceives a maximum of 6 clock cycles on a Serial Clock Line (SCL) of the two-wire serial bus after the first start condition and before the second I2C start condition.

10. The method of claim 1 , further comprising:
changing from the first mode of operation to the second mode of operation after a control sequence is transmitted on the two-wire serial bus.

11. An apparatus comprising:
a first device including:
a bus interface adapted to couple the apparatus to a two-wire serial bus operable to be shared with a plurality of other devices; and
a processing circuit coupled to the bus interface, the processing circuit configured to:
generate a transition number from a set of bits;
convert the transition number into a sequence of symbols, wherein timing information is encoded in transitions between symbols in the sequence of symbols; and
transmit the sequence of symbols on a two-wire serial bus when the two-wire serial bus is operated in a first mode of operation, wherein each transition between consecutive symbols causes a change in a signaling state of the two-wire serial bus,

wherein, while the two-wire serial bus is in the first mode of operation, the sequence of symbols is ignored by a second device coupled to the two-wire serial bus, and
wherein the second device is configured for communicating on the two-wire serial bus using a second mode of operation of the two-wire serial bus.

12. The apparatus of claim 11 , wherein the transition number comprises a twelve digit ternary number.

13. The apparatus of claim 12 , wherein the processing circuit is configured to convert the transition number into the sequence of symbols by:
converting the set of bits to a ternary transition number; and
providing the ternary transition number to a transcoder,
wherein a most significant digit of the ternary transition number is provided to the transcoder first, a least significant digit of the ternary transition number is provided to the transcoder last, and intermediate digits between the most significant digit and the least significant digit are provided to the transcoder in order of decreasing significance.

14. The apparatus of claim 12 , wherein the processing circuit is configured to convert the transition number into the sequence of symbols by:
converting the set of bits to a ternary transition number; and
providing the ternary transition number to a transcoder, wherein a most significant digit of the ternary transition number is provided to the transcoder last.

15. The apparatus of claim 12 , wherein four signaling states are defined for the two-wire serial bus, and wherein each digit of the ternary number selects a next symbol to be transmitted on the two-wire serial bus from one of three available symbols, each of the three available symbols being different from a current symbol being transmitted on the two-wire serial bus.

16. The apparatus of claim 11 , wherein timing information encoded in the sequence of symbols enables a receiver to generate a receive clock from the sequence of symbols.

17. The apparatus of claim 11 , wherein the two-wire serial bus is a multi-purpose bus that supports communications using camera control interface extension (CCIe) protocols when the two-wire serial bus is operated in the first mode of operation, and wherein the two-wire serial bus supports communications using Inter-Integrated Circuit (I2C) protocols in the second mode of operation.

18. The apparatus of claim 17 , wherein the processing circuit is configured to transmit the sequence of symbols on the two-wire serial bus by providing an I2C start condition between sequences of symbols transmitted on the two-wire serial bus in the first mode of operation, wherein timing of the start condition causes a reset of receive logic in a device configured for communications using the I2C protocols.

19. The apparatus of claim 17 , wherein the processing c

Assignees

• Qualcomm Inc

Inventors

• Sengoku Shoichiro
• Wiley George Alan
• Cheung Joseph

Classifications

• G06F13/4295

  using an embedded synchronisation · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title