Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation
US-9213563-B2 · Dec 15, 2015 · US
US9552197B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9552197-B2 |
| Application number | US-201514840083-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 31, 2015 |
| Priority date | Oct 10, 2014 |
| Publication date | Jan 24, 2017 |
| Grant date | Jan 24, 2017 |
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A non-transitory computer-readable recording medium stores therein a program for causing an information processing apparatus to execute a process including analyzing a source program with respect to the information processing apparatus that starts hardware prefetching upon detecting an access to a consecutive area on a main storage device and stops the hardware prefetching upon detecting an end of the access to the consecutive area, specifying an array structure in a loop process as a hardware prefetching target, and generating, from the source program, a machine language program in which the array structure is changed so that a second access occurring next to a first access to the array structure refers to an area being consecutive from the area being referred to by the first access.
Opening claim text (preview).
What is claimed is: 1. A non-transitory computer-readable recording medium having stored therein a program for causing an information processing apparatus to execute a process, the process comprising: analyzing a source program with respect to the information processing apparatus that starts hardware prefetching upon detecting an access to a consecutive area on a main storage device and stops the hardware prefetching upon detecting an end of the access to the consecutive area; specifying an array structure in a loop process as a hardware prefetching target; first generating, from the source program, a first machine language program in which the array structure is not changed; and second generating, from the source program, a second machine language program in which the array structure is changed so that a second access occurring next to a first access to the array structure refers to an area being consecutive from the area being referred to by the first access, the specifying includes specifying the array structure based on profile information about program performance, the profile information being acquired by executing the first machine language program in which the array structure is not changed. 2. The non-transitory computer-readable recording medium according to claim 1 , wherein the profile information contains at least one of an access count to the array structure, a size of an area for storing the array structure and an access status from another variable to the area on a cache memory to store the array structure. 3. The non-transitory computer-readable recording medium according to claim 1 , wherein the specifying specifies the array structure on the basis of a command-based instruction in the source program or an option-based instruction when executing the machine language program. 4. The non-transitory computer-readable recording medium according to claim 1 , wherein the analyzing analyzes the source program when the information processing apparatus starts the hardware prefetching upon detecting an access to an area on the main storage device at a fixed interval of stride width and stops the hardware prefetching upon detecting an end of the access to the area at the fixed interval of stride width, and the specifying specifies the array structure in the loop process as the hardware prefetching target. 5. An information processing apparatus configured to start hardware prefetching upon detecting an access to a consecutive area on a main storage device and to stop the hardware prefetching upon detecting an end of the access to the consecutive area, the information processing apparatus comprising: a processor, and a memory storing a program causing the processor to execute: analyzing a source program; specifying an array structure in a loop process as a hardware prefetching target; first generating, from the source program, a first machine language program in which the array structure is not changed; and second generating, from the source program, a second machine language program in which the array structure is changed so that a second access occurring next to a first access to the array structure refers to an area being consecutive from the area being referred to by the first access, the specifying includes specifying the array structure based on profile information about program performance, the profile information being acquired by executing the first machine language program in which the array structure is not changed. 6. An information processing method comprising: analyzing a source program with respect to an information processing apparatus that starts hardware prefetching upon detecting an access to a consecutive area on a main storage device and stops the hardware prefetching upon detecting an end of the access to the consecutive area; specifying an array structure in a loop process as a hardware prefetching target; first generating, from the source program, a first machine language program in which the array structure is not changed; and second generating, from the source program, a second machine language program in which the array structure is changed so that a second access occurring next to a first access to the array structure refers to an area being consecutive from the area being referred to by the first access, the specifying includes specifying the array structure based on profile information about program performance, the profile information being acquired by executing the first machine language program in which the array structure is not changed.
Reducing the number of cache misses; Data prefetching (cache prefetching G06F12/0862) · CPC title
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