Solid-state imaging device and imaging apparatus

Patent metadata

Field	Value
Publication number	US-9549135-B2
Application number	US-201514858481-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Mar 29, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
an imaging region including a plurality of unit cells arranged in rows and columns, each of the unit cells including at least one light receiving unit, a transfer transistor which transfers a signal charge photoelectrically converted by the at least one light receiving unit, and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge;
a plurality of column signal lines each connected to a source electrode of the amplifying transistor, for receiving an output signal from the amplifying transistor;
a pixel power supply line connected to a drain electrode of the amplifying transistor, for supplying a power supply voltage to the amplifying transistor;
a plurality of constant current source transistors each connected to a different one of the column signal lines; and
a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

2. The solid-state imaging device according to claim 1 ,
wherein the bias circuit includes a voltage-to-current converting circuit having a conversion gain which is positive, the conversion gain being for converting the power supply voltage into a current.

3. The solid-state imaging device according to claim 1 ,
wherein the bias circuit includes:
a first capacitor connected to the power supply voltage; and
a second capacitor connected to a first node to which a voltage other than the power supply voltage is applied, and
an amount of current supplied by each of the constant current source transistors is determined based on a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor.

4. The solid-state imaging device according to claim 3 ,
wherein the first node is set to a ground potential.

5. The solid-state imaging device according to claim 3 ,
wherein the first capacitor includes:
a second node connected to the power supply voltage; and
a third node selectively set to a high impedance state or a low impedance state.

6. The solid-state imaging device according to claim 5 ,
wherein the first capacitor included in the bias circuit comprises a plurality of first capacitors, and
the bias circuit further includes a first control transistor connected to the third node included in at least one of the first capacitors, the first control transistor including a function of changing a ratio of capacitance values of the first capacitors to the capacitance value of the second capacitor.

7. The solid-state imaging device according to claim 6 ,
wherein the bias circuit changes the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor when the amplifying transistors of two or more of the unit cells are simultaneously activated.

8. The solid-state imaging device according to claim 3 ,
wherein the second capacitor included in the bias circuit comprises a plurality of second capacitors, and
the bias circuit further includes a second control transistor connected to a fourth node connected to the at least one of the second capacitors, the fourth node being different from the first node connected to the at least one of the second capacitors, the second control transistor including a function of changing a ratio of the capacitance value of the first capacitor to capacitance values of the second capacitors.

9. The solid-state imaging device according to claim 1 ,
wherein the constant current source transistors and the bias circuit are disposed on physically different sides of the imaging region.

10. The solid-state imaging device according to claim 1 ,
wherein the constant current source transistors and the bias circuit are disposed on a physically same side of the imaging region.

11. A solid-state imaging device comprising:
an imaging region including a plurality of unit cells arranged in rows and columns, each of the unit cells including at least one light receiving unit, a transfer transistor which transfers a signal charge photoelectrically converted by the at least one light receiving unit, and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge;
a plurality of column signal lines each connected to a source electrode of the amplifying transistor, for receiving an output signal from the amplifying transistor;
a pixel power supply line connected to a drain electrode of the amplifying transistor, for supplying a power supply voltage to the amplifying transistor;
a reference signal generating circuit which generates a reference voltage which temporally varies based on a variation in the power supply voltage; and
an analog-to-digital (AD) converting unit which compares a potential of each of the column signal lines with the reference voltage, and converts an analog voltage which is the output signal into a digital voltage.

12. The solid-state imaging device according to claim 11 ,
wherein the reference signal generating circuit includes a third capacitor and a fourth capacitor, and
the reference voltage corresponds to a differential voltage between the power supply voltage and a ground potential, the differential voltage varying at a ratio of a capacitance value of the third capacitor to a capacitance value of the fourth capacitor.

13. The solid-state imaging device according to claim 12 ,
wherein the fourth capacitor includes a plurality of capacitors connected in parallel, and
the reference signal generating circuit (i) sets each of a plurality of ground nodes of the capacitors of the fourth capacitor to a power supply potential or the ground potential, and (ii) adjusts, to a predetermined ratio based on a first control signal, a ratio of a total capacitance value of one or more of the capacitors having the ground nodes set to the power supply potential to a total capacitance value of one or more of the capacitors having the ground nodes set to the ground potential.

14. The solid-state imaging device according to claim 12 ,
wherein the reference signal generating circuit includes:
a ramp signal generating circuit;
an attenuator including: a fifth capacitor having a first terminal connected to an output terminal of the ramp signal generating circuit; and a sixth capacitor connected between a second terminal of the fifth capacitor and a ground potential, the attenuator reducing, at a predetermined rate, an amplitude of a ramp signal by voltage division by the fifth capacitor and the sixth capacitor; and
a buffer circuit which converts a voltage signal of a voltage division point between the fifth capacitor and the sixth capacitor into a voltage signal having a low impedance and outputs the voltage signal having the low impedance,
the fourth capacitor includes a plurality of capacitors connected in parallel, and
the reference signal generating circuit (i) sets each of a plurality of ground nodes of the capacitors of the fourth capacitor to a power supply potential or a ground potential, and (ii) adjusts, to a predetermined ratio based on a second control signal, a ratio of a total capacitance value of one or more of the capacitors having the ground nodes set to the power supply potential to a total capacitance value of one or more of the capacitors having the ground nodes set to the ground potential.

15. The solid-state imaging device according to claim 12 ,
wherein the reference signal generating circuit further includes a first switch for short-circuiting terminals across the fifth capacitor, and
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Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Kito Takayasu
• Amikawa Hiroyuki
• Higuchi Masahiro
• Origasa Kenichi
• Fujinaka Hiroshi

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/76 Primary

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/709

  Circuitry for control of the power supply · CPC title

• H04N25/617 Primary

  for reducing electromagnetic interference, e.g. clocking noise · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title