Memristive akers logic array

Patent metadata

Field	Value
Publication number	US-9548741-B1
Application number	US-201514798485-A
Country	US
Kind code	B1
Filing date	Jul 14, 2015
Priority date	Jul 14, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.

First claim

We claim:

1. A device that comprises a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other;
wherein each primitive logic cell comprises first and second memristive devices that are serially coupled to each other and are of opposite polarities;
wherein each primitive logic cell has two input ports for receiving two primitive logic cell input signals and two output ports for outputting a primitive logic cell output signal;
wherein the first input port is coupled to a first terminal of the first memristive device, the second input port is coupled to a first terminal of the second memristive device, and
wherein the second terminals of the first and second memristive devices are coupled to each other and to the two output ports.

2. The device according to claim 1 further comprising a write circuit that is arranged to set the first and second memristive devices of the multiple primitive logic cells to opposite states during a write phase that precedes a logical operation phase during which the memristive Akers logic array performs a logical operation.

3. The device according to claim 1 further comprising a read circuit that is arranged to read at least one memristive Akers logic array output signal, the at least one memristive Akers logic array output signal is calculated by the memristive Akers logic array during a logical operation phase during which the memristive Akers logic array performs a logical operation.

4. The device according to claim 1 wherein the primitive logic cell output signal is a function of the first and second input signals and of states of the first and second memristive devices.

5. The device according to claim 1 comprising a first group of switches and a second group of switches; wherein the first group of switches couples a write circuit to the two input ports and wherein the second group of switches couples the output port to a read circuit.

6. The device according to claim 5 wherein the first and second groups of switches are transistors.

7. The device according to claim 6 wherein the first and second groups of switches are transistors that are implemented in a silicon layer that is positioned below a metal layer in which the first and second memristive devices of the multiple primitive logic cells are implemented.

8. The device according to claim 1 wherein the memristive Akers logic array is included in a memory unit.

9. The device according to claim 1 wherein the first and second memristive devices of the multiple primitive logic cells are used as memory elements during a storage phase.

10. A method, comprising:
setting states of memristive devices of a memristive Akers logic array during a write phase; wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises first and second memristive devices that are serially coupled to each other and are of opposite polarities;
wherein each primitive logic cell has two input ports for receiving two primitive logic cell input signals and two output ports for outputting primitive logic cell output signals;
wherein the first input port is coupled to a first terminal of the first memristive device, the second input port is coupled to a first terminal of the second memristive device;
wherein the second terminals of the first and second memristive devices are coupled to each other and to the two output ports; and
performing a logical operation by the memristive Akers logic array during a logical operation phase and providing a memristive Akers logic array output signal that is responsive to at least some of the states of the memristive devices and to memristive Akers logic array input signals provided to the memristive Akers logic array during the logical operation phase.

11. The method according to claim 10 further comprising setting, by a write circuit, the first and second memristive devices of the multiple primitive logic cells to opposite states during the write phase.

12. The method according to claim 10 further comprising reading, by a read circuit, at least one memristive Akers logic array output signal, the at least one output signal is the outcome of the logical operation.

13. The method according to claim 10 wherein the primitive logic cell output signals are a function of the first and second primitive logic cell input signals and of states of the first and second memristive devices.

14. The method according to claim 10 comprising coupling, by a first group of switches, a write circuit to the two input ports and coupling, by a second group of switches the primitive logic cell output ports to a read circuit.

15. The method according to claim 14 wherein the first and second groups of switches are transistors.

16. The method according to claim 15 wherein the first and second groups of switches are transistors that are implemented in one or more silicon layers that are positioned below metal layers in which the memristors are implemented in a silicon layer that is positioned below a metal layer in which the first and second memristive devices of the multiple primitive logic cells are implemented.

17. The method according to claim 16 wherein the memristive Akers logic array is included in a memory unit.

18. The method according to claim 16 comprising storing in the first and second memristive devices of the multiple primitive logic cells of the memristive Akers logic array information during a storage phase.

Assignees

• Technion Res & Dev Foundation

Inventors

• Kvatinsky Shahar
• Kolodny Avinoam
• Hanein Yifat

Classifications

• H03K19/094

  using field-effect transistors · CPC title

• H03K19/02

  using specified components ({H03K19/0005 - H03K19/0021}, H03K19/003 - H03K19/0175 take precedence) · CPC title

• H03K19/1776 Primary

  for memories · CPC title

• H03K19/17708

  using an AND matrix followed by an OR matrix, i.e. programmable logic arrays · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title