Balun based phase inverter using replica load

Patent metadata

Field	Value
Publication number	US-9548704-B1
Application number	US-201514984042-A
Country	US
Kind code	B1
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Aspects of the present invention include a circuit that includes an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other. The circuit further includes an actual switched amplification stage configured to direct one of the balun output signals to a phase inverter output, and a replica switched amplification stage connected in parallel with the actual switched amplification stage, wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of the balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit.

First claim

What is claimed is:

1. A circuit comprising:
an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other;
an actual switched amplification stage configured to direct one of the balun output signals to the phase inverter output; and
a replica switched amplification stage connected in parallel with the actual switched amplification stage;
wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of the balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit, and
wherein the actual switched amplification stage and the replica switched amplification stage each comprises an amplification circuit of transistors and switches, and wherein the circuit further comprises a control device that controls a state of the transistors and the switches during operation of the circuit.

2. The circuit of claim 1 wherein the circuit comprises a phase inverter circuit.

3. The circuit of claim 1 further comprising two matching networks, a first matching network connected between a first one of the two output signals from the input balun circuit and a first input to both the actual switched amplification stage and the replica switched amplification stage, a second matching network connected between a second one of the two output signals from the input balun circuit and a second input to both the actual switched amplification stage and the replica switched amplification stage.

4. The circuit of claim 3 wherein each of the two matching networks is configured to match the load impedance of both the actual switched amplification stage and the replica switched amplification stage to the impedance of the input balun circuit.

5. The circuit of claim 1 wherein the input balun circuit comprises one of an active balun circuit and a passive balun circuit.

6. The circuit of claim 1 wherein the input balun circuit comprises a passive balun circuit from a group comprising a Marchand type balun circuit and a Lumped Element type balun circuit.

7. A method comprising:
providing an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other;
providing an actual switched amplification stage configured to direct one of the balun output signals to the a phase inverter output; and
providing a replica switched amplification stage connected in parallel with the actual switched amplification stage;
wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit, and
wherein the actual switched amplification stage and the replica switched amplification stage each comprises an amplification circuit of transistors and switches, and wherein the method further comprises providing a control device that controls a state of the transistors and the switches during operation of the circuit.

8. The method of claim 7 wherein the circuit comprises a phase inverter circuit.

9. The method of claim 7 further comprising providing two matching networks, a first matching network connected between a first one of the two output signals from the input balun circuit and a first input to both the actual switched amplification stage and the replica switched amplification stage, a second matching network connected between a second one of the two output signals from the input balun circuit and a second input to both the actual switched amplification stage and the replica switched amplification stage.

10. The method of claim 9 wherein each of the two matching networks is configured to match the load impedance of both the actual switched amplification stage and the replica switched amplification stage to the impedance of the input balun circuit.

11. The method of claim 7 wherein the input balun circuit comprises one of an active balun circuit and a passive balun circuit.

12. The method of claim 7 wherein the input balun circuit comprises a passive balun circuit from a group comprising a Marchand type balun circuit and a Lumped Element type balun circuit.

13. A phase inverter circuit comprising:
an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other;
an actual switched amplification stage configured to direct one of the balun output signals to the a phase inverter output;
a replica switched amplification stage connected in parallel with the actual switched amplification stage; and
two matching networks, a first matching network connected between a first one of the two output signals from the input balun circuit and a first input to both the actual switched amplification stage and the replica switched amplification stage, a second matching network connected between a second one of the two output signals from the input balun circuit and a second input to both the actual switched amplification stage and the replica switched amplification stage;
wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of the balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit.

14. The phase inverter circuit of claim 13 wherein each of the two matching networks is configured to match the load impedance of both the actual switched amplification stage and the replica switched amplification stage to the impedance of the input balun circuit.

15. The phase inverter circuit of claim 13 wherein the input balun circuit comprises one of an active balun circuit and a passive balun circuit.

16. The phase inverter circuit of claim 13 wherein the input balun circuit comprises a passive balun circuit from a group comprising a Marchand type balun circuit and a Lumped Element type balun circuit.

17. The phase inverter circuit of claim 13 wherein the actual switched amplification stage and the replica switched amplification stage each comprises an amplification circuit of transistors and switches.

18. The phase inverter circuit of claim 17 wherein the phase inverter circuit further comprises a control device that controls a state of the transistors and the switches during operation of the phase inverter circuit.

Assignees

• IBM

Inventors

• Ben-Yishay Roee
• Katz Oded

Classifications

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F1/56 Primary

  Modifications of input or output impedances, not otherwise provided for · CPC title

• H03F2200/06

  A balun, i.e. balanced to or from unbalanced converter, being present at the input of an amplifier · CPC title