Method of making a monolithic three dimensional NAND string using a select gate etch stop layer

Patent metadata

Field	Value
Publication number	US-9548313-B2
Application number	US-201514725466-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 30, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

First claim

What is claimed is:

1. A method of making a monolithic three dimensional NAND string, comprising:
forming a select gate layer of a third material over a major surface of a substrate;
forming a stack of alternating first material and second material layers over the select gate layer, wherein the first material, the second material and the third material are different from each other;
etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching;
further etching the select gate layer using a second etch chemistry, wherein the second etch chemistry is different from the first etch chemistry; and
forming a semiconductor channel and at least one charge storage region of the NAND string in the stack;
wherein at least one end portion of the semiconductor channel extends substantially perpendicular to the major surface of the substrate; and
wherein the at least one charge storage region is located adjacent to semiconductor channel.

2. The method of claim 1 , wherein:
the at least one opening comprises a plurality of memory openings;
the step of further etching the select gate layer comprises further etching the plurality of memory openings to form a plurality of extended memory openings which extend through the select gate layer; and
forming the semiconductor channel and at least one charge storage region of the NAND string in the stack comprises forming a respective semiconductor channel of a plurality of semiconductor channels and a respective charge storage region of a plurality of charge storage regions in each extended memory opening of the plurality of extended memory openings.

3. The method of claim 2 , wherein the select gate layer comprises a sacrificial layer, the first material comprises a first insulating material and the second material comprises a second sacrificial material.

4. The method of claim 3 , further comprising:
etching a trench through the stack to the sacrificial layer using the first etch chemistry after the step of forming the semiconductor channel and at least one charge storage region;
further etching the trench through the sacrificial layer using the second etch chemistry;
selectively removing the sacrificial layer and the second sacrificial material layers though the trench;
forming a metal or metal alloy select gate electrode of the NAND string through the trench in a location previously occupied by the sacrificial layer;
forming a plurality of metal or metal alloy control gate electrodes of the NAND string through the trench in locations previously occupied by the second sacrificial material layers; and
forming a source line in the trench.

5. The method of claim 4 , wherein:
the sacrificial layer comprises polysilicon;
the metal or metal alloy select gate electrode comprises a tungsten or a tungsten and titanium nitride select gate electrode;
the plurality of metal or metal alloy control gate electrodes comprise a plurality of tungsten or tungsten and titanium nitride control gate electrodes;
the first material comprises silicon oxide;
the second material comprises silicon nitride;
the at least one charge storage region comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric which are located between the semiconductor channel and the plurality of metal or metal alloy control gate electrodes;
forming the semiconductor channel and at least one charge storage region of the NAND string in the stack comprises:
forming the respective semiconductor channel of the plurality of semiconductor channels, a respective tunnel dielectric and a respective charge trapping layer or floating gate of the plurality of charge storage regions in each extended memory opening of the plurality of extended memory openings; and
forming a respective blocking dielectric either in each extended memory opening of the plurality of extended memory openings or through the trench between the steps of selectively removing the sacrificial second insulating material layers and forming the plurality of metal or metal alloy control gate electrodes;

forming the source line in the trench comprises forming an insulating layer in the trench and forming a tungsten or a tungsten and titanium nitride source line in the trench over the insulating layer;
the insulating layer electrically isolates the control gate electrodes from the source line; and
the source line electrically contacts a portion of the semiconductor channel of the NAND string located in the substrate.

6. The method of claim 2 , wherein the select gate layer comprises a metal or metal alloy select gate electrode, the first material comprises a first insulating material and the second material comprises a sacrificial second insulating material.

7. The method of claim 6 , further comprising:
etching a trench through the stack to the select gate electrode using the first etch chemistry after the step of forming the semiconductor channel and at least one charge storage region;
further etching the trench through the select gate electrode using the second etch chemistry;
selectively removing the sacrificial second insulating material layers though the trench;
forming a plurality of metal or metal alloy control gate electrodes of the NAND string through the trench in locations previously occupied by the sacrificial second insulating material layers; and
forming a source line in the trench;
wherein a material of the plurality of metal or metal alloy control gate electrodes is different from a material of the select gate electrode.

8. The method of claim 7 , wherein:
the metal or metal alloy select gate electrode comprises a tungsten silicide select gate electrode;
the plurality of metal or metal alloy control gate electrodes comprise a plurality of tungsten or tungsten and titanium nitride control gate electrodes;
the first material comprises silicon oxide;
the second material comprises silicon nitride;
the at least one charge storage region comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric which are located between the semiconductor channel and the plurality of metal or metal alloy control gate electrodes;
forming the semiconductor channel and at least one charge storage region of the NAND string in the stack comprises:
forming the respective semiconductor channel of the plurality of semiconductor channels, a respective tunnel dielectric and a respective charge trapping layer or floating gate of the plurality of charge storage regions in each extended memory opening of the plurality of extended memory openings; and
forming a respective blocking dielectric either in each extended memory opening of the plurality of extended memory openings or through the trench between the steps of selectively removing the sacrificial second insulating material layers and forming the plurality of metal or metal alloy control gate electrodes;

forming the source line in the trench comprises forming an insulating layer in the trench and forming a tungsten or a tungsten and titanium nitride source line in the trench over the insulating layer;
the insulating layer electrically isolates the control gate electrodes from the source line; and
the source line electrically contacts a portion of the semiconductor channel of the NAND string located in the substrate.

9. The method of claim 1 , wherein:
the first material comprises a first insulating material;
the second material comprises a sacrificial second insulating material;
the select gate layer comprises a sacrificial polysilicon layer; and
the at least one opening compr

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Yada Shinsuke
• Fujino Shigehiro
• Kimura Hajime
• Terahara Masanori
• Honma Ryoichi
• Ogawa Hiroyuki
• Itou Ryousuke

Classifications

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title