Chip package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9548265-B2
Application number	US-201615138119-A
Country	US
Kind code	B2
Filing date	Apr 25, 2016
Priority date	Apr 27, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

First claim

What is claimed is:

1. A chip package, comprising:
a chip having a substrate, a first electrical pad, and a protection layer, wherein the substrate has a first surface and an opposite second surface, the protection layer is located on the first surface, and the first electrical pad is located in the protection layer, and the substrate has a through hole, and the protection layer has a concave hole, such that the first electrical pad is exposed through the concave hole and the through hole;
an isolation layer located on the second surface, a sidewall of the through hole, and a sidewall of the concave hole; and
a redistribution layer comprising:
a connection portion located on the isolation layer and in electrical contact with the first electrical pad; and
a passive component portion located on the isolation layer that is on the second surface, wherein an end of the passive component portion is connected to the connection portion that is on the second surface.

2. The chip package of claim 1 , wherein shapes of the passive component portion comprise U-shape, planar spiral-shape, and three-dimensional spiral-shape.

3. The chip package of claim 1 , wherein the chip has a conducting wire that is in the protection layer, and the conducting wire is connected to the first electrical pad to another adjacent first electrical pad.

4. The chip package of claim 1 , further comprising:
a barrier layer located on the redistribution layer and on the isolation layer that is on the second surface.

5. The chip package of claim 4 , wherein the barrier layer has an opening to expose the connection portion, and the chip package further comprises:
a conductive structure located on the connection portion in the opening of the barrier layer, such that the conductive structure is electrically connected to the first electrical pad.

6. The chip package of claim 5 , wherein the conductive structure is a solder ball or a conductive bump.

7. The chip package of claim 1 , wherein the chip further comprises:
a second electrical pad located in the protection layer, wherein the first electrical pad is located between the second electrical pad and the substrate.

8. The chip package of claim 7 , wherein the protection layer has an opening to expose the second electrical pad.

9. The chip package of claim 8 , further comprising:
a conductive structure located on the second electrical pad that is in the opening of the protection layer.

10. The chip package of claim 8 , further comprising:
a conductive layer located on a surface of the protection layer facing away from the substrate and on the second electrical pad that is in the opening of the protection layer.

11. The chip package of claim 10 , further comprising:
a barrier layer covering the conductive layer and the protection layer.

12. The chip package of claim 11 , wherein the barrier layer has an opening to expose the conductive layer, and the chip package further comprises:
a conductive structure located on the conductive layer that is in the opening of the barrier layer, such that the conductive structure is electrically connected to the second electrical pad.

13. The chip package of claim 4 , wherein the chip package has a cavity, and the cavity is located between the barrier layer and the connection portion that is in the through hole.

14. The chip package of claim 1 , further comprising:
a magnetic component surrounded by the passive component portion.

15. A manufacturing method of a chip package, comprising:
using a temporary adhesive layer to attach a carrier to a wafer, wherein the wafer has a substrate, an electrical pad, and a protection layer, and the substrate has a first surface and an opposite second surface, and the protection layer is located on the first surface, and the electrical pad is located in the protection layer;
etching the second surface of the substrate, thereby forming a through hole in the substrate;
etching the protection layer that is in the through hole, thereby forming a concave hole in the protection layer and exposing the electrical pad through the concave hole and the through hole;
forming an isolation layer on the second surface, a sidewall of the through hole, and a sidewall of the concave hole;
forming a redistribution layer on the isolation layer and the electrical pad; and
patterning the redistribution layer for simultaneously forming a connection portion and a passive component portion in the redistribution layer, wherein the connection portion is located on the isolation layer and in electrical contact with the electrical pad, and the passive component portion is located on the isolation layer that is on the second surface, and an end of the passive component portion is connected to the connection portion that is on the second surface.

16. The manufacturing method of claim 15 , further comprising:
grinding the second surface of the substrate, thereby reducing a thickness of the substrate.

17. The manufacturing method of claim 15 , further comprising:
forming a barrier layer on the redistribution layer and the isolation layer that is on the second surface; and
patterning the barrier layer for forming an opening, thereby exposing the connection portion through the opening.

18. The manufacturing method of claim 17 , further comprising:
forming a conductive structure on the connection portion that is in the opening of the barrier layer, such that the conductive structure is electrically connected to the electrical pad.

19. The manufacturing method of claim 18 , further comprising:
cutting the carrier, the wafer, the isolation layer and the barrier layer.

20. The manufacturing method of claim 19 , further comprising:
removing adhesion of the temporary adhesive layer, and
removing the carrier for forming the chip package.

21. The manufacturing method of claim 15 , wherein forming the redistribution layer on the isolation layer and on the electrical pad comprises:
connecting two ends of at least one conductive device to two connecting points of a conducting ring respectively;
disposing the wafer having the isolation layer into the conducting ring;
immersing the conducting ring in a plating solution; and
energizing the conducting ring for forming the redistribution layer that is to be patterned on the isolation layer, wherein a partial current passing through one of the connecting points transmits to the other connecting point through the conductive device.

22. The manufacturing method of claim 21 , wherein the conducting ring has a top surface, a sidewall, and a supporting surface which are sequentially connected, and disposing the wafer having the isolation layer into the conducting ring further comprises:
disposing the wafer on the supporting surface, such that the wafer is surrounded by the sidewall, wherein the first surface faces the supporting surface.

23. The manufacturing method of claim 22 , further comprising:
disposing the connecting points and the conductive device on the top surface of the conducting ring.

24. The manufacturing method of claim 15 , wherein the forming the redistribution layer on the isolation layer and the electrical pad comprises:
movably connecting two connecting points of two ends of at least one conductive piece to a ring-shaped track of a conducting ring, wherein the conductive piece overlaps a portion of the conducting ring;
disposing the wafer having the isolation layer in the conducting r

Assignees

• Xintec Inc

Inventors

• Ho Yen-Shih
• Chang Shu-Ming
• Shen Hsing-Lung
• Su Yu-Hao
• Wu Kuan-Jung
• Cheng Yi

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10P72/7606

  characterised by edge clamping, e.g. clamping ring · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title