Micro device transfer head array

Patent metadata

Field	Value
Publication number	US-9548233-B2
Application number	US-201615052767-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	May 25, 2012
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect. A dielectric layer covers a top surface of each mesa structure.

First claim

What is claimed is:

1. A bipolar micro device transfer head array comprising:
a base substrate;
an array of electrostatic transfer heads, each electrostatic transfer head including a pair of silicon electrodes, and a dielectric material covering a top surface of the pair of silicon electrodes;
wherein each silicon electrode is doped.

2. The micro device transfer head array of claim 1 , wherein the dielectric material covers the top surface of each pair of silicon electrodes for each electrostatic transfer head in the array of electrostatic transfer heads.

3. The micro device transfer head array of claim 1 , wherein the array of electrostatic transfer heads comprises:
a first array of silicon electrodes in electrical connection with a first bus interconnect; and
a second array of silicon electrodes in electrical connection with a second bus interconnect.

4. The micro device transfer head array of claim 3 , wherein the array of electrostatic transfer heads comprises:
a first plurality of trace interconnects electrically connecting the first array of silicon electrodes with the first bus interconnect; and
a second plurality of trace interconnects electrically connecting the second array of silicon electrodes with the second bus interconnect.

5. The micro device transfer head array of claim 4 , wherein the first and second plurality of trace interconnects are silicon trace interconnects, and the first and second bus interconnects are silicon bus interconnects.

6. The micro device transfer head array of claim 4 , wherein the first plurality of trace interconnects run parallel with the second plurality of trace interconnects.

7. The micro device transfer head array of claim 6 , wherein the first array of silicon electrodes extend from the first plurality of trace interconnects and the second array of silicon electrodes extend form the second plurality of trace interconnects parallel with the first array of silicon electrodes.

8. The micro device transfer head array of claim 7 , further comprising an array of dielectric joints between the first array of silicon electrodes and the second array of silicon electrodes.

9. The micro device transfer head array of claim 3 , further comprising a first voltage source connection in electrical connection with the first bus interconnect, and a second voltage source connection in electrical connection with the second bus interconnect.

10. The micro device transfer head array of claim 9 , wherein the first voltage source connection comprises a via extending through the base substrate, and the second voltage source connection comprises a via extending through the base substrate.

11. The micro device transfer head array of claim 1 , wherein each electrostatic transfer head is configured to pick up an individual micro device of 1 to 100 μm scale.

12. The micro device transfer head of claim 1 , wherein the dielectric material covering the top surface of the pair of silicon electrodes has a thickness between 0.5-10 μm.

13. The micro device transfer head of claim 1 , wherein each silicon electrode includes a silicon electrode lead and a silicon mesa structure.

14. The micro device transfer head of claim 13 , wherein the mesa structure is less than 20 μm thick.

15. The micro device transfer head of claim 13 , wherein the mesa structure is less than 10 μm thick.

16. The micro device transfer head of claim 1 , further comprising an oxide layer on a bottom surface of the pair of silicon electrodes.

17. The micro device transfer head of claim 1 , wherein the dielectric material comprises an oxide selected from the group consisting of SiO 2 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , and RuO 2 .

18. The micro device transfer head of claim 1 , wherein each silicon electrode is doped with an n-dopant.

19. The micro device transfer head of claim 1 , wherein each silicon electrode is doped with phosphorus.

20. The micro device transfer head of claim 1 , wherein each silicon electrode is formed in a doped silicon device layer with a resistivity of less than 0.1 ohm-centimeter.

Assignees

• Luxvue Tech Corp
• Apple Inc

Inventors

• Golda Dariusz
• Bibl Andreas

Classifications

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title