Method of adjusting channel widths of semiconductive devices

Patent metadata

Field	Value
Publication number	US-9548216-B1
Application number	US-201514809270-A
Country	US
Kind code	B1
Filing date	Jul 26, 2015
Priority date	Jul 26, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.

First claim

What is claimed is:

1. A method of adjusting channel widths of semiconductive devices, comprising:
providing a substrate divided into a first region and a second region, wherein the substrate comprises a plurality of fins disposed within the first region and the second region and an isolating region disposed between adjacent fins;
performing a first implantation process on the fins within the first region;
performing a second implantation process on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy;
simultaneously removing part of the fins within the first region and the second region to form a plurality of first recesses within the first region and a plurality of second recesses within the second region, wherein a depth of each of the first recesses is greater than a depth of each of the second recesses; and
simultaneously forming a first epitaxial layer to fill up each first recess and forming a second epitaxial layer to fill up each second recess.

2. The method of adjusting channel widths of semiconductive devices of claim 1 , wherein before removing the fins, a top surface of each fin within the first region and within the second region is aligned with a top surface of the isolating region.

3. The method of adjusting channel widths of semiconductive devices of claim 2 , wherein a top surface of the first epitaxial layer and a top surface of the second epitaxial layer are both aligned with the top surface of the isolating region.

4. The method of adjusting channel widths of semiconductive devices of claim 1 , further comprising:
simultaneously removing a first depth of the isolating region within the first region and within the second region to make the first epitaxial layer and the second epitaxial layer protrude over a top surface of the remaining isolating region.

5. The method of adjusting channel widths of semiconductive devices of claim 4 , wherein after removing the first depth of the isolating region, part of each fin within the first region protrudes over the top surface of the remaining isolating region.

6. The method of adjusting channel widths of semiconductive devices of claim 1 , further comprising:
removing a second depth of the isolating region within the first region to make the first epitaxial layer protrude over a top surface of the remaining isolating region within the first region; and
removing a third depth of the isolating region within the second region to make the second epitaxial layer protrude over a top surface of the remaining isolating region within the second region, wherein the second depth is different from the third depth.

7. The method of adjusting channel widths of semiconductive devices of claim 6 , wherein the entire first epitaxial layer protrudes over the top surface of the remaining isolating region within the first region, and the entire second epitaxial layer protrudes over the top surface of the remaining isolating region within the second region.

8. The method of adjusting channel widths of semiconductive devices of claim 6 , wherein after removing the third depth of the isolating region, part of each fin within the second region protrudes over the top surface of the remaining isolating region.

9. The method of adjusting channel widths of semiconductive devices of claim 1 , wherein a thickness of the first epitaxial layer is greater than a thickness of the second epitaxial layer.

10. The method of adjusting channel widths of semiconductive devices of claim 1 , wherein the dopant species comprises p-type dopants or n-type dopants.

11. The method of adjusting channel widths of semiconductive devices of claim 1 , wherein each of the first recesses is defined by the isolation region within the first region and the remaining fins adjacent to the isolation region within the first region.

12. The method of adjusting channel widths of semiconductive devices of claim 1 , wherein each of the second recesses is defined by the isolation region within the second region and the remaining fins adjacent to the isolation region within the second region.

Assignees

• United Microelectronics Corp

Inventors

• Chen Yu-Te
• Tseng Chia-Hsun
• Liou En-Chiuan
• Hsu Chiung-Lin
• Tsai Meng-Lin
• Yang Jan-Fu
• Hung Yu-Ting
• Su Shin-Feng

Classifications

• H10P50/642 Primary

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171 Primary

  being group IV material · CPC title

• H01L21/2253

  Electricity · mapped topic