Ion trap apparatus and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9548179-B2
Application number	US-201514878375-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Oct 14, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An ion trap device includes a substrate over which at least one central DC electrode, an RF electrode and at least one side electrode are disposed. The central DC electrode includes a DC connector pad and a DC rail connected to the DC connector pad. The RF electrode includes at least one RF rail located adjacent to the DC rail and an RF pad connected to the at least one RF rail. The RF electrode is disposed between the central DC electrode and the side electrode. At least one pair of electrodes among the central DC electrode, the RF electrode and the side electrode have round corners facing each other.

First claim

The invention claimed is:

1. An ion trap device, comprising:
a substrate;
at least one central DC electrode disposed over the substrate and comprising:
a DC connector pad, and
a DC rail connected to the DC connector pad;

an RF electrode disposed over the substrate and comprising:
at least one RF rail located adjacent to the DC rail, and
an RF pad connected to the at least one RF rail; and

at least one side electrode disposed over the substrate, wherein
the RF electrode is disposed between the central DC electrode and the side electrode, and
at least one pair of electrodes among the central DC electrode, the RF electrode and the side electrode have round corners facing each other.

2. The ion trap device of claim 1 , wherein
the central DC electrode comprises a first central DC electrode having a first DC rail and a second central DC electrode having a second DC rail,
the first DC rail and the second DC rail are spaced apart from each other to form a trap region therebetween, and
an entire thickness of the substrate is removed at a region corresponding to the trap region.

3. The ion trap device of claim 2 , wherein the RF electrode has a round corner at an inner side facing the trap region.

4. The ion trap device of claim 1 , wherein the at least one side electrode includes a plurality of side electrodes disposed at predetermined intervals in a longitudinal direction of the RF electrode.

5. The ion trap device of claim 1 , further comprising:
an insulator disposed between (i) the at least one central DC electrode, the RF electrode and the at least one side electrode and (ii) the substrate,
wherein each of the at least one central DC electrode, the RF electrode and the at least one side electrode has a larger width than that of the insulator disposed thereunder.

6. The ion trap device of claim 1 , further comprising:
an insulator disposed between (i) the at least one central DC electrode, the RF electrode and the at least one side electrode and (ii) the substrate,
a conductive film between the insulator and the substrate,
wherein the conductive film comprises
a first portion connecting the side electrode to a corresponding bonding part, and
a second portion separated from the first portion and connected to the ground.

7. The ion trap device of claim 1 , wherein all corners of at least one of the RF electrode, the central DC electrode and the side electrode are round corners.

8. The ion trap device of claim 1 , wherein the substrate is a semiconductor substrate.

9. A method of fabricating an ion trap device, the method comprising:
depositing an insulator over a substrate;
depositing a conductive film over the insulator; and
forming electrode patterns including an RF electrode, a central DC electrode and a side electrode; and
wherein the forming of the electrode patterns includes:
masking the electrode patterns on the deposited conductive film; and
etching remnants of the deposited conductive film left from the masking, and

wherein each of the RF electrode, the central DC electrode and the side electrode has a shape of round corners.

10. The method of claim 9 , wherein at least one pair of electrodes among the central DC electrode, the RF electrode and the side electrode have the respective round corners facing each other.

11. The method of claim 9 , further comprising:
removing an entire thickness of the substrate at a region corresponding to a trap region,
wherein
the central DC electrode comprises a first central DC electrode having a first DC rail and a second central DC electrode having a second DC rail, and
the first DC rail and the second DC rail are spaced apart from each other by the trap region therebetween.

12. The method of claim 9 , further comprising:
reducing a width of the insulator under each of the central DC electrode, the RF electrode and the side electrode to be smaller than a width of the overlying central DC electrode, RF electrode or side electrode.

13. The method of claim 12 , wherein said reducing comprises wet etching.

14. The method of claim 9 , wherein all corners of at least one of the RF electrode, the central DC electrode and the side electrode are round corners.

15. The method of claim 9 , wherein the substrate is a semiconductor substrate.

Assignees

• Sk Telecom Co Ltd
• Univ Seoul Nat R & Db Found

Inventors

• Cho Dongil
• Kim Taehyun
• Yoon Jongkeon
• Choi Byoungdoo
• Hong Seokjun
• Lee Minjae

Classifications

• H01J9/14

  of non-emitting electrodes · CPC title

• H01J49/0013 Primary

  Miniaturised spectrometers, e.g. having smaller than usual scale, integrated conventional components · CPC title

• H01J3/00 Primary

  Details of electron-optical or ion-optical arrangements common to two or more basic types of discharge tubes or lamps · CPC title

• H01J49/422

  Two-dimensional RF ion traps (ion guides without mass selection H01J49/062) · CPC title

• H01J49/065

  having stacked electrodes, e.g. ring stack, plate stack · CPC title