Integrated circuit device body bias circuits and methods

Patent metadata

Field	Value
Publication number	US-9548086-B2
Application number	US-201514799715-A
Country	US
Kind code	B2
Filing date	Jul 15, 2015
Priority date	Mar 15, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

First claim

What is claimed is:

1. A system, comprising:
a plurality of blocks, each block comprising a different integrated circuit function and each including transistors formed therein;
a bias circuit corresponding to each block and configured to receive a control value unique to the block, each bias circuit configured to generate a local body bias voltage for transistors of its block in response to the control value of the block;
a collapse circuit corresponding to each block, each collapse circuit configured to couple the bodies of its transistors to a collapse voltage that tracks a power supply voltage, in response to at least one collapse enable signal for the block; and
an event detect circuit corresponding to each block, each event detect circuit configured to activate the collapse enable signal of its block in response to at least one local event signal and in response to at least one global event signal;
wherein
the at least one local event signal is generated in the corresponding block and the at least one global event signal is generated outside of the block in response to at least one predetermined event;
the blocks include a processor circuit block comprising at least one processor, a static or dynamic RAM block, and analog circuit block; and
the local body bias voltage for transistors of the processor block and the local body bias voltage for transistors of the memory are generated independently.

2. The system of claim 1 , wherein:
each bias circuit receives a multi-bit control value comprising at least process variation, gate length variation, and threshold voltage variation in chip and includes a digital to analog converter (DAC) that converts the control value into an analog value.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Clark Lawrence T
• Kidd David A
• Kuo Augustine

Classifications

• G05F3/205

  Substrate bias-voltage generators (for static stores G11C5/146) · CPC title

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G11C5/146

  Substrate bias generators (G11C5/141 takes precedence) · CPC title

• G06F30/30

  Circuit design · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title