Interrupt supervision system, processing system and method for interrupt supervision

Patent metadata

Field	Value
Publication number	US-9547546-B2
Application number	US-201214382593-A
Country	US
Kind code	B2
Filing date	Mar 12, 2012
Priority date	Mar 12, 2012
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device. The interrupt controller device is arranged to receive, on the plurality of interrupt request input lines, a plurality of corresponding interrupt requests and to provide, on the at least one output line, the plurality of interrupt requests to the processing device in a sequence generated by the interrupt controller device depending on one or more priorities assigned to the interrupt requests; and one or more interrupt checker devices, each being arranged to receive a reception indication when the interrupt controller device receives, on a selected one of the plurality of interrupt request lines, a corresponding selected interrupt request, and to provide a corresponding error indication when an output of the corresponding selected interrupt request from the interrupt controller device on the at least one output line is not confirmed within a latency period assigned to the corresponding selected interrupt request, wherein the assigned latency period begins when the interrupt checker device receives the reception indication.

First claim

The invention claimed is:

1. An interrupt supervision system, comprising:
a plurality of interrupt request input lines;
an interrupt request output line;
an interrupt controller device connected to said interrupt request input lines, for receiving, on said plurality of interrupt request input lines, a plurality of interrupt requests, said interrupt controller device being arranged to generate a sequence of interrupt requests from said plurality of interrupt requests depending on one or more priorities assigned to said interrupt requests and to output said plurality of interrupt requests in said sequence on said interrupt request output line;
said interrupt supervision system further comprising an interrupt checker device connected to a selected one of said interrupt request input lines, to detect that said interrupt controller device has received on said selected interrupt request input line a selected interrupt request, and connected to said interrupt request output line;
said interrupt checker device being arranged to provide an error indication when an output of said selected interrupt request on said interrupt request output line has not been confirmed within a latency period assigned to said selected interrupt request, said latency period beginning when said interrupt checker device detects that said interrupt controller device has received said selected interrupt request.

2. The interrupt supervision system as claimed in claim 1 , comprising a memory unit arranged to store interrupt request selection information for the interrupt checker device.

3. The interrupt supervision system as claimed in claim 2 , comprising a connection between said interrupt checker device and said plurality of interrupt request input lines which can be activated or deactivated, and said interrupt checker device is arranged to activate or deactivate said connection depending on said interrupt request selection information.

4. The interrupt supervision system as claimed in claim 1 , wherein for said interrupt checker device said assigned latency period ends with a first occurrence subsequent to receiving said selected interrupt request of outputting of an interrupt request on said interrupt request output line.

5. The interrupt supervision system as claimed in claim 1 , wherein said interrupt checker device comprises a timer unit arranged to measure said assigned latency period.

6. The interrupt supervision system as claimed in claim 1 , wherein said interrupt checker device is arranged to monitor the output of the interrupt controller device and said confirmation is received when the interrupt checker observes an output of said corresponding selected interrupt request on said interrupt request output line.

7. The interrupt supervision system as claimed in claim 1 , wherein said interrupt checker device is connectable to said processing device and arranged to receive from said processing device an indication confirming completion of an interrupt service routine associated with said corresponding selected interrupt service request.

8. The interrupt supervision system as claimed in claim 7 , wherein said interrupt checker device is connectable to said processing device via a data bus of a processing system.

9. The interrupt supervision system as claimed in claim 7 , wherein said interrupt controller device comprises a status input line connectable to receive indications confirming completion of interrupt service routines corresponding to interrupt service requests sent to said processing device on said interrupt request output line and wherein said interrupt checker device is connected to said status input line.

10. A processing system, comprising
a processing device; and
an interrupt supervision system coupled to the processing device, the interrupt supervision system comprising:
a plurality of interrupt request input lines;
an interrupt request output line;
an interrupt controller device connected to said interrupt request input lines, the interrupt controller to receive a plurality of interrupt requests on said plurality of interrupt request input lines, to generate a sequence of interrupt requests in response to said plurality of interrupt requests and priorities assigned to said interrupt requests, and to output said plurality of interrupt requests in said sequence on said interrupt request output line; and
an interrupt checker device connected to the interrupt request input lines and to said interrupt request output line, to detect that said interrupt controller device has received a selected interrupt request on said selected interrupt request input line, to provide an error indication in response to an output of said selected interrupt request on said interrupt request output line has not been confirmed within a latency period assigned to said selected interrupt request, wherein the latency period is assigned to the selected interrupt request based on the priority of the selected interrupt request, said latency period beginning when said interrupt checker device detects that said interrupt controller device has received said selected interrupt request.

11. The processing system as claimed in claim 10 , comprising a fault management device connected to said interrupt supervision system, to receive said error indication from said interrupt supervision system.

12. The processing system as claimed in claim 10 , wherein said processing device comprises two processing cores operable in lock-step mode.

13. The processing system as claimed in claim 10 , implemented as a single integrated circuit, such as a system-on-a-chip or a system in a package.

14. The processing system as claimed in claim 10 , wherein said processing system is a safety critical system.

15. The processing system of claim 10 , wherein said interrupt checker device comprises a timer unit arranged to measure said assigned latency period.

16. A method for interrupt supervision in an interrupt supervision system, said method comprising:
receiving, by an interrupt controller device, over a plurality of interrupt request input lines a plurality of interrupt requests;
generating, by said interrupt controller device, a sequence of interrupt requests from said plurality of interrupt requests depending on priorities assigned to said interrupt requests;
outputting, by said interrupt controller device, on a output line said plurality of interrupt requests to a processing device in said sequence;
detecting, by a interrupt checker device, that said interrupt controller device has received, on a selected one of said plurality of interrupt request lines, a selected interrupt request; and
providing, by said interrupt checker device, an error indication when an output of said selected interrupt request from said interrupt controller device on said interrupt request output line is not confirmed within a latency period assigned to said selected interrupt request, wherein said assigned latency period begins when said interrupt checker device detects that said interrupt controller device has received the selected interrupt request.

17. The method of claim 16 , further comprising:
measuring, at a timer unit of the interrupt checker device, the assigned latency period.

18. The method of claim 16 , further comprising:
storing, at a memory unit, interrupt request selection information for the interrupt checker device.

19. The method of claim 17 , further comprising:
activating or deactivating, a connection between said interrupt checker device and said plurality of interrupt request input lines, depe

Assignees

• Baumeister Markus
• Freeman Jeffrey L
• Nxp Usa Inc

Inventors

• Baumeister Markus
• Freeman Jeffrey L

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title