Multi-core image processor for portable device

Patent metadata

Field	Value
Publication number	US-9544451-B2
Application number	US-201213620879-A
Country	US
Kind code	B2
Filing date	Sep 15, 2012
Priority date	Jul 12, 1997
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A portable handheld device including a CPU for processing a script; a multi-core processor for processing an image; an input buffer for receiving data for processing by the multi-core processor, the input buffer being provided under the control of the multi-core processor to send data thereto; and an output buffer for receiving data processed by the multi-core processor, the output buffer being provided under the control of the multi-core processor to receive data therefrom. The multi-core processor comprises a plurality of micro-coded processing units. The CPU is configured with authority to clear and query the input and output buffers.

First claim

I claim:

1. A processor for a portable handheld device including a card reader, the processor comprising on a shared wafer:
a card reader interface for receiving an instruction script from a data card inserted in the card reader;
a CPU for processing the instruction script;
a multi-core processor for processing an image, the multi-core processor having a plurality of processing units each including a microcode RAM; and
a memory interface separate from the card reader interface and configured to receive image data from an external memory for processing by the multi-core processor,
wherein the CPU loads each microcode RAM with a microcode program to effect execution of the instruction script.

2. A processor as claimed in claim 1 , further comprising a data cache integrated with the CPU and multi-core processor as a system-on-chip device, the data cache being shared by the plurality of processing units via a first data bus.

3. A processor as claimed in claim 2 , wherein each of the processing units includes an individual input buffer and an individual output buffer, each individual input buffer and each individual output buffer being connected to the first data bus to thereby achieve connection of each processing unit with the data cache.

4. A processor as claimed in claim 2 , wherein each processing unit includes an ALU.

5. A processor as claimed in claim 4 , further comprising a second date bus connecting each ALU in a ring topology, the second data bus effecting parallel connection of the plurality of processing units, wherein the second data bus is separate from the first data bus.

6. A processor as claimed in claim 4 , further comprising a common synchronization register shared by the plurality of processing units, the common synchronization register for synchronizing one or more of the processing units to function as a single process.

7. A processor as claimed in claim 1 , further comprising a flash memory for storing microcode, wherein the CPU reads the flash memory to obtain microcode for loading into the microcode RAM of each processing unit.

8. A processor for a portable device, the processor comprising:
a first image sensor interface configured to receive first image data from a first image sensor of the portable device;
a second image sensor interface configured to receive second image data from a second image sensor of the portable device;
a CPU for processing an instruction script; and
a multi-core processor for processing the first image data, the multi-core processor having a plurality of processing units each including a microcode RAM
wherein the first image sensor interface, the second image sensor interface, the CPU and the multi-core processor are integrated on a common wafer substrate.

9. The processor of claim 8 , wherein the first image sensor interface is separate from the second image sensor interface.

10. The processor of claim 8 , further comprising a data cache integrated with the CPU and the multi-core processor as a system-on-chip device, the data cache being shared by the plurality of processing units via a data bus.

11. The processor of claim 10 , wherein each of the processing units includes an individual input buffer and an individual output buffer, each individual input buffer and each individual output buffer being connected to the data bus to thereby achieve connection of each processing unit with the data cache.

12. The processor of claim 11 , further comprising a common synchronization register shared by the plurality of processing units, the common synchronization register for synchronizing one or more of the processing units to function as a single process.

13. A processor for a portable device, the processor comprising:
a multi-core processor including a plurality of processing units;
a plurality of image sensor interfaces configured to receive image sensor data wherein the multi-core processor and the plurality of image sensor interfaces are disposed on a common wafer substrate, and each image sensor interface of the plurality of image sensor interfaces are separately disposed on the common wafer substrate;
a CPU for processing an instruction script, wherein each processing unit of the plurality of processing units includes a microcode RAM;
a data cache integrated with the CPU and shared by the plurality of processing units via a first data bus;
a second data bus separate from the first data bus and configured to connect the plurality of processing units in parallel, wherein the plurality of processing units each include an ALU, the second data bus connects to the ALU of each of the plurality of processing units, and the second data bus connects the ALU of each of the plurality of processing units in a ring topology.

14. The processor of claim 13 , wherein the CPU, the data cache, the first data bus and the second data bus are disposed on the common wafer substrate.

15. The processor of claim 13 , wherein the plurality of image sensor interfaces includes a first image sensor interface and a second image sensor interface, and the first image sensor interface is configured to receive first image data related to a first image captured by a first image sensor, and the second image sensor interface is configured to receive second image data related to a second image captured by a second image sensor.

Assignees

• Silverbrook Kia
• Google Inc

Inventors

• Silverbrook Kia

Classifications

• H10W42/405

  using active circuits · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N23/843

  Demosaicing, e.g. interpolating colour pixel values · CPC title

• B41J2/14 Primary

  Structure thereof {only for on-demand ink jet heads} · CPC title

• B41J2/17546

  electronically · CPC title