Method and apparatus for inserting idle bytes in a data stream

Patent metadata

Field	Value
Publication number	US-9544237-B1
Application number	US-201414522306-A
Country	US
Kind code	B1
Filing date	Oct 23, 2014
Priority date	Oct 23, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

In a method of transferring a plurality of data packets from a media access control (MAC) layer device to a physical layer (PHY) device, interpacket gaps (IPGs) having a number N I =N block *n−(p mod Nblock) of idle bytes are inserted between packets, where p is an integer denoting a length of a data packet in bytes, N block is a blocking size in bytes, and n is an integer initialized to one and incremented every time q data bytes of the data packet are transferred. The parameter n is reset to one in connection with each IPG insertion.

First claim

What is claimed is:

1. A method of transferring, from a media access control (MAC) layer device to a physical layer (PHY) device, a plurality of data packets, the method comprising:
setting, at the MAC layer device, a parameter n to have an initial value of one;
transferring, from the MAC layer device to the PHY device via a media-independent interface, the plurality of data packets, including incrementing the parameter n for every q data bytes that are transferred, wherein q is a finite integer; and
for each data packet transferred,
setting, at the MAC layer device, a number of idle bytes N I of an interpacket gap (IPG) having N I =N block *n−(p mod N block ) idle bytes, wherein p is an integer denoting a length of the data packet in bytes and N block is a blocking size in bytes,
inserting, by the MAC layer device, the N I bytes of the IPG after data bytes in the data packet are transferred in order to create a time gap between the data packet and a subsequent data packet, and
resetting, at the MAC layer device, the parameter n to one.

2. The method of claim 1 , wherein N block =8.

3. The method of claim 2 , wherein an average value of N I is less than eight.

4. The method of claim 3 , wherein an average value of N I is 4.5 for randomly varying data packet lengths.

5. The method of claim 2 , further comprising maintaining n=1 when there are no data packets to output.

6. The method of claim 1 , further comprising determining the parameter q based on a rate at which alignment markers are to be inserted.

7. The method of claim 6 , further comprising determining the parameter q further based on a number of virtual lanes to be utilized.

8. The method of claim 6 , further comprising determining the parameter q further based on a maximum number of idle bytes to be removed due to a difference between a clock of the MAC layer device and a clock of the PHY device.

9. An apparatus, comprising:
a media access control (MAC) layer device;
a physical layer (PHY) device coupled to the MAC layer device;
wherein the MAC layer device includes one or more integrated circuit devices configured to:
set a parameter n to have an initial value of one,
transfer, from the MAC layer device to the PHY device via a media-independent interface, a plurality of data packets,
increment the parameter n for every q data bytes that are transferred, wherein q is a finite integer, and
for each data packet transferred,
set a number of idle bytes N I for an interpacket gap (IPG) having N I =N block *n−(p mod N block ) idle bytes, wherein p is an integer denoting a length of the data packet in bytes and N block is a blocking size in bytes,
insert the N I bytes of the IPG after data bytes in the data packet are transferred in order to create a time gap between the data packet and a subsequent data packet, and
reset the parameter n to one.

10. The apparatus of claim 9 , wherein N block =8.

11. The apparatus of claim 10 , wherein an average value of N I is less than eight.

12. The apparatus of claim 11 , wherein an average value of N I is 4.5 for randomly varying data packet lengths.

13. The apparatus of claim 10 , wherein the one or more integrated circuits are further configured to maintain n=1 when there are no data packets to output.

14. The apparatus of claim 9 , wherein the one or more integrated circuits are further configured to determine q based on a rate at which alignment markers are to be inserted.

15. The apparatus of claim 14 , wherein the one or more integrated circuits are further configured to determine q further based on a number of virtual lanes to be utilized.

16. The apparatus of claim 14 , wherein the one or more integrated circuits are further configured to determine q further based on a maximum number of idle bytes to be removed due to a difference between a clock of the MAC layer device and a clock of the PHY device.

17. A non-transitory computer readable storage medium having computer program instructions stored thereon that, when executed by one or more processors, cause the one or more processors to implement a method of transferring, from a media access control (MAC) layer device to a physical layer (PHY) device, a plurality of data packets, the method comprising:
setting a parameter n to have an initial value of one;
transferring, from the MAC layer device to the PHY device via a media-independent interface, the plurality of data packets, including incrementing the parameter n for every q data bytes that are transferred, wherein q is a finite integer; and
for each data packet transferred,
setting a number of idle bytes N I of an interpacket gap (IPG) having N I =N block *n−(p mod N block ) idle bytes, wherein p is an integer denoting a length of the data packet in bytes and N block is a blocking size in bytes,
inserting the N I bytes of the IPG after data bytes in the data packet are transferred in order to create a time gap between the data packet and a subsequent data packet, and
resetting the parameter n to one.

18. The non-transitory computer readable storage medium claim 17 , wherein N block =8.

19. The non-transitory computer readable storage medium claim 17 , further comprising computer program instructions stored thereon that, when executed by one or more processors, cause the one or more processors to determine q further based on a number of virtual lanes to be utilized.

20. The non-transitory computer readable storage medium claim 17 , further comprising computer program instructions stored thereon that, when executed by one or more processors, cause the one or more processors to determine q further based on a maximum number of idle bytes to be removed due to a difference between a clock of the MAC layer device and a clock of the PHY device.

Assignees

• Marvell Int Ltd

Inventors

• Lo William

Classifications

• H04L47/12

  Avoiding congestion; Recovering from congestion · CPC title

• H04L47/22

  Traffic shaping · CPC title

• H04L47/31 Primary

  by tagging of packets, e.g. using discard eligibility [DE] bits · CPC title