Techniques to perform forward error correction for an electrical backplane

US9544089B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9544089-B2
Application numberUS-201514698102-A
CountryUS
Kind codeB2
Filing dateApr 28, 2015
Priority dateJan 4, 2006
Publication dateJan 10, 2017
Grant dateJan 10, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A media independent interface and circuitry of a forward error correction (FEC) sublayer are provided, the circuitry of the FEC sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer. The FEC sublayer include an encoder having a reverse gearbox, a compressor coupled to said reverse gearbox, a selector coupled to said compressor, a parity generator coupled to said compressor, a multiplexer coupled to said compressor, selector and said parity generator, a scrambler coupled to said multiplexer, and a pseudo-noise generator coupled to said scrambler.

First claim

Opening claim text (preview).

The invention claimed is: 1. An apparatus, comprising: a media independent interface; and circuitry of a forward error correction (FEC) sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer, the FEC sublayer comprising an encoder having: a reverse gearbox; a compressor coupled to said reverse gearbox; a selector coupled to said compressor; a parity generator coupled to said compressor; a multiplexer coupled to said compressor, selector and said parity generator; a scrambler coupled to said multiplexer; and a pseudo-noise generator coupled to said scrambler.

Assignees

Inventors

Classifications

  • Error control for data other than payload data, e.g. control data · CPC title

  • Joint error correction and other techniques (H03M13/31 and H03M13/33 take precedence) · CPC title

  • Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

  • Arrangements at the transmitter end · CPC title

  • Error detection codes · CPC title

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Frequently asked questions

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What does patent US9544089B2 cover?
A media independent interface and circuitry of a forward error correction (FEC) sublayer are provided, the circuitry of the FEC sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer. The FEC sublayer include an encoder having a reverse gearbox, a compressor coupled to said reverse gearbox, a selector …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H03M13/33. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).