Method and system for optimizing short term stability of a clock pulse

Patent metadata

Field	Value
Publication number	US-9544078-B2
Application number	US-201214367934-A
Country	US
Kind code	B2
Filing date	Dec 20, 2012
Priority date	Dec 23, 2011
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A system for optimizing short-term stability of a clock source clock pulse synchronized with a long-term stable reference-clock transmits clock numbers of a first reference clock to the clock source, between an initialization time and several times within a data-packet network. The clock pulse is adjusted by controlling a difference between clock numbers of the first reference clock received in the clock source and clock numbers of the first reference clock between the initialization time and the reception times of the clock numbers of the first reference clock. Clock numbers of a second reference clock are transmitted to the clock source with the clock number of at least one second reference-clock source at individual times. The maximum difference between the first and the second reference clock is known. The difference between the clock pulse of the clock source and each second reference clock is limited to an adjustable threshold value.

First claim

The invention claimed is:

1. A method comprising:
transmitting clock-cycle numbers of a first reference clock signal of a first reference-clock source to a clock source between an initialization time and several times within a data-packet network, wherein the clock source is synchronized with a first long-term stable reference-clock source;
adjusting a clock pulse of the clock source by controlling a difference between clock-cycle numbers of the first reference clock signal received in the clock source and clock-cycle numbers of the first reference clock signal between the initialization time and the respective reception times of the clock-cycle numbers of the first reference clock signal, wherein the frequency of a frequency oscillator integrated in a phase control is used for matching the received clock-cycle numbers of the first reference clock signal;
transmitting clock-cycle numbers of at least one second reference clock signal of a data packet, which receives the clock-cycle number from at least one second, free-running reference-clock source at individual times to the clock source; and
limiting the difference between the clock pulse of the clock source and each second reference clock signal to a first adjustable threshold value.

2. The method according to claim 1 , wherein the clock pulse of the clock source in a superposed frequency control is controlled in such a manner that the difference between the clock pulse of the clock source and the second reference clock signal is less than the first adjustable threshold value.

3. The method according to claim 1 , wherein the difference between the frequency with which the difference between the clock pulse of the clock source and the first reference clock signal is controlled within a phase-locked loop and the second reference clock signal is limited to a second adjustable threshold value.

4. The method according to claim 1 , wherein the clock-cycle numbers of the second reference clock signal of the respective at least one second reference-clock source are each transmitted at periodic times, and a second reference clock signal of the respective at least one second reference-clock source is determined from the received clock-cycle numbers of the second reference clock signal of the respective second reference-clock source in the clock source.

5. The method according to claim 1 , wherein the second reference clock signal of a single, second reference-clock source is determined in the clock source.

6. The method according to claim 1 , wherein the second reference clock signal is determined by averaging the second reference clock signals in the clock source generated respectively from the at least one second reference-clock source.

7. The method according to claim 6 , wherein the at least one second reference-clock source comprises a temperature-compensated quartz oscillator.

8. The method according to claim 1 , wherein, in the case of a failure of the data-packet network, the second reference clock signal is determined continuously from the received clock-cycle numbers of the second reference clock signal by means of regression, and the clock pulse of the clock source is determined within a frequency control with the determined second reference clock signal as the target frequency value.

9. The method according to claim 1 , wherein, in the case of a failure of the data-packet network, the first reference clock signal is determined by means of regression from the clock-cycle numbers of the first reference clock signal received until the failure, and the clock pulse of the clock source is determined within a frequency control with the determined first reference clock signal as the target frequency value.

10. The method according to claim 1 , wherein the rate with which the clock-cycle numbers of the first reference clock signal are transmitted to the clock source is increased, as soon as the difference between the clock pulse of the clock source and the second reference clock signal exceeds a third adjustable threshold value.

11. The method according to claim 1 , wherein the maximum difference between the first and the second reference clock signals of the clock source is known or specified.

12. A system comprising:
a first processing device configured to determine clock-cycle numbers of a first reference clock signal of a first reference-clock source between an initialization time and several times,
wherein the first processing device is further configured to transmit, via a data-packet network, the clock-cycle numbers of the first reference clock signal to a third processing device;
a second processing device configured to determine clock-cycle numbers of a second reference clock signal between the initialization time and the respective several times,
wherein the second processing device is further configured to transmit, via a second network, the clock-cycle numbers of the second reference clock signal determined respectively from each second reference-clock source to the third processing device,
wherein the third processing device is configured to determine a clock pulse based on the received clock-cycle numbers of the first reference clock signal and the received clock-cycle numbers of the second reference clock signal, wherein the clock source is synchronized with a first long-term stable reference-clock source, and
wherein the frequency of a frequency oscillator integrated in a phase control is used for matching the received clock-cycle numbers of the first reference clock signal.

13. The system according to claim 12 , wherein the second reference-clock source comprises a temperature-compensated quartz oscillator.

14. The system according to claim 12 , wherein the second network is a local high-speed network.

15. The system according to claim 12 , wherein a maximum difference between the first reference clock signal and the second reference clock signal of the clock source is known or specified.

Assignees

• Rohde & Schwarz

Inventors

• Herzog Norman

Classifications

• H04J3/0667

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• H04J3/0697 Primary

  Synchronisation in a packet node · CPC title

• H04N21/242

  Synchronisation processes, e.g. processing of PCR [Programme Clock References] {(arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18)} · CPC title

• H04J3/0658

  Clock or time synchronisation among packet nodes · CPC title

• H04J3/0635

  Clock or time synchronisation in a network (timer in protocols H04L69/28) · CPC title