Semiconductor memory device and a method of operating the same

Patent metadata

Field	Value
Publication number	US-9543952-B2
Application number	US-201414460764-A
Country	US
Kind code	B2
Filing date	Aug 15, 2014
Priority date	Oct 29, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A semiconductor memory device includes a ZQ calibration unit configured to generate an output high level voltage (VOH) code according to a VOH control code obtained from a result of comparing a reference voltage with a first VOH; and an output driver configured to generate a data signal having a second VOH determined by the VOH code. The VOH control code includes a pull-up VOH control code and a pull-down VOH control code and the VOH code includes a pull-up VOH code and a pull-down VOH code.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a ZQ calibration unit configured to generate an output high level voltage (VOH) code according to a VOH control code obtained from a result of comparing a reference voltage with a first VOH, wherein the reference voltage is calibrated according a VOH difference between different memory devices; and
an output driver configured to generate a data signal having a second VOH determined by the VOH code,
wherein the VOH control code comprises a pull-up VOH control code and a pull-down VOH control code and the VOH code comprises a pull-up VOH code and a pull-down VOH code.

2. The semiconductor memory device of claim 1 , wherein the ZQ calibration unit comprises:
a first calibration unit configured to generate the pull-up VOH code, which determines a current generated by a pull-up driver included in the output driver, based on a first target VOH determined by the pull-up VOH control code; and
a second calibration unit configured to generate the pull-down VOH code, which determines a resistance of a pull-down driver included in the output driver, based on a second target VOH determined by the pull-down VOH control code.

3. The semiconductor memory device of claim 2 , wherein the first calibration unit comprises:
a pull-up VOH control block configured to generate the first target VOH;
a first comparator configured to output a first comparison result by comparing the first target VOH with a voltage of a first node;
a first code generator configured to generate the pull-up VOH code based on the first comparison result;
a replica pull-up driver configured to generate a first current flowing across the first node according to the pull-up VOH code; and
a replica system on chip (SOC) on die termination (ODT) resistor configured to determine the voltage of the first node according to the first current.

4. The semiconductor memory device of claim 3 , wherein the second calibration unit comprises:
a pull-down VOH control block configured to generate the second target VOH;
a second comparator configured to output a second comparison result by comparing the second target VOH with a voltage of a second node;
a second code generator configured to generate the pull-down VOH code based on the second comparison result; and
a replica pull-down driver configured to determine the voltage of the second node according to the pull-down VOH code.

5. The semiconductor memory device of claim 4 , wherein the replica SOC ODT resistor has a resistance determined by the pull-down VOH code.

6. The semiconductor memory device of claim 5 , wherein the voltage of the second node is determined by a resistor outside the semiconductor memory device and the replica pull-down driver.

7. The semiconductor memory device of claim 1 , wherein the VOH control code is generated by an internal test mode signal of the semiconductor memory device or a VOH change request signal provided from outside the semiconductor memory device.

8. The semiconductor memory device of claim 1 , further comprising a pre-driver configured to generate a pull-up driving signal and a pull-down driving signal according to the VOH code and internal data,
wherein the output driver comprises a pull-up driver configured to generate a current determined by the pull-up driving signal and a pull-down driver configured to have a resistance determined by the pull-down driving signal.

9. A semiconductor memory device, comprising:
a data output circuit configured to perform ZQ calibration according to an output high level voltage (VOH) change request signal or a test mode signal and output a data signal whose VOH has been changed,
the data output circuit including a ZQ calibration control unit configured to generate a VOH control code corresponding to information of the VOH change request signal or the test mode signal, the information indicating whether to increase or decrease the VOH, wherein the information of the VOH change request signal or the test mode signal is indicative of a difference between a first reference voltage of a first memory device and a second reference voltage of a second memory device exceeding a first threshold.

10. The semiconductor memory device of claim 9 , wherein the data signal is output from a DQ terminal.

11. The semiconductor memory device of claim 10 , wherein the VOH change request signal is generated by a memory controller configured to receive the data signal output from the DQ terminal.

12. The semiconductor memory device of claim 9 , wherein the data output circuit further comprises a ZQ calibration unit configured to generate a pull-up VOH code or a pull-down VOH code in response to the VOH control code.

13. The semiconductor memory device of claim 12 , wherein the data output circuit further comprises a pre-driver configured to generate a pull-up driving signal and a pull-down driving signal in response to the pull-up VOH code, the pull-down VOH code and data.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ki Won

Classifications

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C29/021

  in voltage or current generators · CPC title