Differential signal reversion and correction circuit and method thereof

Patent metadata

Field	Value
Publication number	US-9543949-B2
Application number	US-201514627391-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Jan 24, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

First claim

The invention claimed is:

1. A differential signal reversion and correction circuit, comprising:
two interconnected nodes; and
a data frame sending module and a reversion control signal generating module disposed between the two interconnected nodes,
the data frame sending module, including:
a first input port, a second input port, a second output port, a third input port, and a third output port, the first input port is connected to a P line and an N line through a first buffer, the second input port, the second output port, the third input port, and the third output port are connected to each other in parallel and then are connected to the P line and the N line respectively; and

the reversion control signal generating module, including:
a second buffer connected to the P line and the N line,
a comparator connected in series to the second buffer, and
a control link, the control link including an uplink and a downlink, wherein
the uplink is a first control switch, wherein an input of the first control switch is disposed at a configuring module which is positioned between the buffer and the comparator, the first control switch is connected in series to the configuring module, and an output of the first control switch is connected to the P line and the N line respectively, and
the downlink is a second control switch, wherein an input of the second control switch is disposed between the buffer and the comparator, and an output of the second control switch is connected to the P line and the N line respectively.

2. A method of differential signal reversion and correction, comprising:
when a link goes into a mode of link detection and reversion and correction:
generating, by a data frame sending module, a corresponding logic sequence and finishing sending the corresponding logic sequence,
receiving, by a receiving side, the corresponding logic sequence, and
comparing, with a comparator, and processing the corresponding logic sequence received by the receiving side and performs corresponding feedback or checking, thereby achieving link detection and differential correction purpose;

notifying a reversion control signal generating module of a comparing result from the comparator; and
generating, by the reversion control signal generating module, a corresponding control signal which controls the correctness of data receiving and controls whether the link performs a reversion operation.

3. The method of claim 2 , wherein when the link goes into a mode of link detection and reversion and correction further comprises:
generating, by the data frame sending module, a logic “1” sequence;
sending the sequence, by a second input port, a second output port, a third input port, and a third output port;
in the receiving side, controlling, by a configuring module, a control switch to pull-down a signal;
detecting a pull-down result by the second input port, the second output port, the third input port, and the third output port, wherein
if the pull-down result is a logic “0”, the link is connected, otherwise the link is failed; and
if the link is connected, generating, by the data frame sending module, a logic “1” or logic “0” sequence, and
sending the sequence by the first input port.

4. The method of claim 3 , further comprising:
in the receiving side, comparing, by the comparator, the received logic “1” sequence or logic “0” sequence with a high level and a low level, wherein if the logic “1” sequence is sent, the sequence is compared with the high level, and if the logic “0” sequence is sent, the sequence is compared with the low level; and
if the logic “1” sequence is sent, comparing the logic “1” sequence with the high level in the receiving side, when the comparison result shows the logic “1” sequence and the high level are the same, outputting, by the comparator, logic “0” and no differential signal reversion occurs in the transmission link, and P-N is adopted for data recovery; when the comparison result shows the logic “1” sequence and the high level are different, outputting, by the comparator, logic “1”, notifying the reversion control signal generating module, and controlling a data receiving module to reverse and control the link, and N-P is adopted for data recovery.

5. The method of claim 3 , further comprising:
when the transmission link adopts multi-channel transmission, controlling, by a control state machine, the interconnection nodes to enter into a link detection and reversion correction mode, wherein all the channels perform channel detection and reversion correction respectively, the channel that has not performed reversion adopts P-N manner to recover data in the receiving side, and the channel that has performed reversion adopts N-P manner to recover data in the receiving side.

Assignees

• Inspur Electronic Information Industry Co Ltd

Inventors

• Wang Endong
• Hu Leijun
• Li Rengang

Classifications

• H03K19/00 Primary

  Logic circuits, i.e. having at least two inputs acting on one output (circuits for computer systems using fuzzy logic G06N7/02); Inverting circuits · CPC title

• H03K19/018585 Primary

  programmable · CPC title

• H03K19/018592

  with a bidirectional operation · CPC title