RRAM device

Patent metadata

Field	Value
Publication number	US-9543511-B2
Application number	US-201514645878-A
Country	US
Kind code	B2
Filing date	Mar 12, 2015
Priority date	Mar 12, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer;
a bottom electrode disposed over the lower metal interconnect layer and comprising a lower portion surrounded by a bottom dielectric layer and an upper portion that is wider than the lower portion, wherein the bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer;
a RRAM dielectric having a variable resistance, disposed on the bottom electrode;
a top electrode disposed over the RRAM dielectric; and
a top dielectric layer disposed over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode and overlying a top surface of the top electrode.

2. The integrated circuit device of claim 1 , wherein the upper portion of the bottom electrode has a tapered sidewall covered by the top dielectric layer, and the tapered sidewall has a first tilt angle in a range of from about 65° to about 75° with respect to a lower surface of the upper portion.

3. The integrated circuit device of claim 2 , wherein the lower portion of the bottom electrode is tapered with a second tilt angle of about 60° to about 70° with respect to the first tilt angle.

4. The integrated circuit device of claim 2 , wherein a sidewall of the RRAM dielectric is aligned with the tapered sidewall of the upper portion of the bottom electrode.

5. The integrated circuit device of claim 1 , wherein the bottom dielectric layer abuts the lower portion of the bottom electrode and the top dielectric layer abuts the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

6. The integrated circuit device of claim 1 , wherein a ratio of an isolation distance between the top and bottom electrodes to a lateral dimension of the top electrode is in a range of from about 1:7 to about 1:13.

7. The integrated circuit device of claim 1 , wherein the bottom electrode comprises at least two layers of conductive material including titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

8. The integrated circuit device of claim 1 , wherein the RRAM dielectric comprises one or more of hafnium aluminum oxide (HfAlO), hafnium oxide (HfO x ), aluminum oxide (AlO x ), or tantalum oxide (TaO x ).

9. The integrated circuit device of claim 1 , wherein the top and bottom dielectric layers comprises silicon carbide (SiC).

10. The integrated circuit device of claim 1 , further comprising:
a capping layer disposed between the RRAM dielectric and the top electrode, having a sidewall vertically aligned with a sidewall of the top electrode, wherein the capping layer has a lower concentration of oxygen than the RRAM dielectric; and
a hard mask disposed between the top electrode and the top dielectric layer and having a sidewall vertically aligned with sidewalls of the capping layer and the RRAM dielectric.

11. The integrated circuit device of claim 10 , wherein the capping layer comprises titanium (Ti), hafnium (Hf), platinum (Pt), or ruthenium (Ru).

12. An integrated circuit device, comprising:
a substrate comprising a transistor with a source region and a drain region;
a lower metal interconnect layer disposed over the substrate and electrically coupled to the drain region of the transistor through a series of contacts and vias;
a resistive random access memory (RRAM) cell disposed over the lower metal interconnect layer and comprising a bottom electrode, a RRAM dielectric arranged over the bottom electrode, and a top electrode arranged over the RRAM dielectric; and
an upper metal interconnect layer disposed over the RRAM cell and electrically coupled to the top electrode of the RRAM cell through a via;
wherein the bottom electrode comprises an upper portion with a trapezoid shape and a lower portion with a smaller lateral dimension than the upper portion;
wherein the top electrode has a cuboid shape with a lateral dimension smaller than a minimum lateral dimension of the upper portion of the bottom electrode.

13. The integrated circuit device of claim 12 , further comprising:
a bottom dielectric layer having a curved sidewall that abuts a corresponding curved sidewall of the lower portion of the bottom electrode; and
a top dielectric layer disposed over the bottom dielectric layer and continuously extending along tapered sidewalls of the upper portion of the bottom electrode and the RRAM dielectric, wherein the top dielectric layer overlies a top surface of the RRAM dielectric not covered by the top electrode, and extends along a sidewall of the top electrode and overlies a top surface of the top electrode.

14. The integrated circuit device of claim 13 , wherein a tilt angle of the tapered sidewalls of the upper portion of the bottom electrode and the RRAM dielectric is in a range of from about 65° to about 75°.

15. The integrated circuit device of claim 12 , wherein a ratio of an isolation distance between the top and bottom electrodes to a lateral dimension of the top electrode is in a range of from about 1:7 to about 1:13.

16. A method of forming an integrated circuit device, comprising:
forming a bottom electrode layer over a substrate, a RRAM dielectric layer over the bottom electrode layer, and a top electrode layer over the RRAM dielectric layer;
patterning the top electrode layer to form a top electrode;
depositing a sidewall polymer mask along a sidewall of the top electrode; and
patterning the bottom electrode layer according to the sidewall polymer mask to form a bottom electrode having a sidewall that is inwardly tilted;
wherein the bottom electrode is formed by forming a via opening through a bottom dielectric layer followed by forming the bottom electrode layer into the via opening and over the bottom dielectric layer, such that the bottom electrode is formed to comprise a lower portion surrounded by the bottom dielectric layer and an upper portion that is wider than the lower portion.

17. The method of claim 16 , wherein the RRAM dielectric layer is etched concurrent to depositing the sidewall polymer mask by using hydrogen bromide (HBr) and one or more additional reactant gases.

18. The method of claim 16 , wherein patterning the top electrode layer, depositing the sidewall polymer mask, and patterning the bottom electrode layer, are performed in-situ.

19. The method of claim 16 , wherein the sidewall polymer mask is partially etched concurrent to patterning the bottom electrode layer.

20. The method of claim 16 , wherein the bottom electrode layer is formed to include a lower portion and an upper portion that is wider than the lower portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sung Fu-Ting
• Wu Chang-Ming
• Chen Hsia-Wei
• Liu Shih-Chang
• Chu Wen-Ting
• Liao yu-wen

Classifications

• H01L45/146

  Electricity · mapped topic

• H01L45/1233 Primary

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic