Magnetic memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9543505-B2
Application number	US-201514729710-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Sep 12, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A memory device includes a magnetic tunnel junction comprising a first free layer, a pinned layer, and a tunnel barrier layer disposed between the first free layer and the pinned layer, wherein the first free layer comprises a first free magnetic pattern adjacent to the tunnel barrier layer, and a second free magnetic pattern spaced apart from the tunnel barrier layer with the first free magnetic pattern interposed therebetween, wherein the second free magnetic pattern contacts the first free magnetic pattern, wherein the first and second free magnetic patterns include boron (B), wherein a boron content of the first free magnetic pattern is higher than a boron content of the second free magnetic pattern, and wherein the boron content of the first free magnetic pattern is in a range of about 25 at % to about 50 at %.

First claim

What is claimed is:

1. A memory device comprising:
a magnetic tunnel junction including: a first free layer; a pinned layer; and a tunnel barrier layer between the first free layer and the pinned layer, wherein
the first free layer includes a first free magnetic pattern adjacent to the tunnel barrier layer and a second free magnetic pattern spaced apart from the tunnel barrier layer with the first free magnetic pattern therebetween,
the second free magnetic pattern contacts the first free magnetic pattern,
the first and second free magnetic patterns include boron (B),
a boron content of the first free magnetic pattern is higher than a boron content of the second free magnetic pattern,
the boron content of the first free magnetic pattern is in a range of about 25 at % to about 50 at %, and
the pinned layer includes a first pinned layer adjacent to the tunnel barrier layer, the first pinned layer including,
a polarization enhancement magnetic pattern adjacent to the tunnel barrier layer; and
a middle magnetic pattern spaced apart from the tunnel barrier layer with the polarization enhancement magnetic pattern therebetween, the middle magnetic pattern contacting the polarization enhancement magnetic pattern, and the middle portion having a boron content higher than a boron content of the polarization enhancement magnetic pattern and a boron content of the second pinned layer.

2. The memory device of claim 1 , wherein the boron content of the second free magnetic pattern is in a range of about 20 at % to about 35 at %.

3. The memory device of claim 1 , wherein a thickness of the first free magnetic pattern is substantially equal to a thickness of the second free magnetic pattern.

4. The memory device of claim 1 , wherein a thickness of the first free layer is in a range of about 10 Å to about 20 Å.

5. The memory device of claim 1 , wherein the first and second free magnetic patterns include cobalt-iron-boron (CoFeB).

6. The memory device of claim 1 , wherein the pinned layer further includes:
a second pinned layer spaced apart from the tunnel barrier layer with the first pinned layer therebetween,
wherein the first and second pinned layers include boron, and
wherein a boron content of the first pinned layer is higher than a boron content of the second pinned layer.

7. The memory device of claim 6 , wherein the boron content of the middle magnetic pattern is substantially equal to the boron content of the first free magnetic pattern.

8. The memory device of claim 6 , wherein the middle magnetic pattern includes iron-boron (FeB).

9. The memory device of claim 1 , wherein the magnetic tunnel junction further includes:
a non-magnetic metal layer adjacent to the first free layer; and
a second free layer spaced apart from the first free layer with the non-magnetic metal layer therebetween,
wherein the boron contents of the first and second free magnetic patterns are higher than a boron content of the second free layer.

10. The memory device of claim 9 , wherein a thickness of the first free layer is substantially equal to or greater than a thickness of the second free layer.

11. The memory device of claim 9 , wherein the magnetic tunnel junction further comprises:
a capping layer spaced apart from the non-magnetic metal layer with the second free layer therebetween,
wherein the capping layer contacts one surface of the second free layer to induce interfacial perpendicular magnetic anisotropy (i-PMA).

12. The memory device of claim 1 , wherein the magnetic tunnel junction is on a substrate, and
wherein the pinned layer is between the substrate and the tunnel barrier layer.

13. The memory device of claim 1 , wherein the magnetic tunnel junction is on a substrate, and
wherein the first free layer is between the substrate and the tunnel barrier layer.

14. The memory device of claim 1 , wherein the boron content of the first free magnetic pattern is about 40 at %.

15. A memory device comprising:
a magnetic tunnel junction including: a free layer, a pinned layer, and a tunnel barrier layer between the free layer and the pinned layer, wherein
the free layer includes a first free magnetic pattern adjacent to the tunnel barrier layer and a second free magnetic pattern spaced apart from the tunnel barrier layer with the first free magnetic pattern therebetween,
the second free magnetic pattern contacts the first free magnetic pattern,
the first and second free magnetic patterns include cobalt-iron-boron (CoFeB),
a boron content of the first free magnetic pattern is higher than a boron content of the second free magnetic pattern, and
the pinned layer includes,
a polarization enhancement magnetic pattern adjacent to the tunnel barrier layer; and
a middle magnetic pattern spaced apart from the tunnel barrier layer with the polarization enhancement magnetic pattern therebetween, the middle magnetic pattern contacting the polarization enhancement magnetic pattern, the middle magnetic pattern including iron-boron (FeB), and the middle portion having a boron content that is substantially equal to the boron content of the first free magnetic pattern.

Assignees

• Park Sang Hwan
• Kim Kwangseok
• Kim Keewon
• Kim Jae Hoon
• Lee Joonmyoung
• Samsung Electronics Co Ltd

Inventors

• Park Sang Hwan
• Kim Kwangseok
• Kim Keewon
• Kim Jae Hoon
• Lee Joonmyoung

Classifications

• H01L29/82

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic