Thin film transistor driving backplane and manufacturing method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-9543415-B2
Application number	US-201314362971-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Sep 27, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The manufacturing method may comprise: manufacturing a backplane base disposed with a plurality of active device structures; disposing an electrode layer on the backplane base; and manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process. According to the embodiment of the present invention, the electrode layer is manufactured into a plurality of source electrodes, drain electrodes and pixel electrodes, integrally disposed with the drain electrode, by one time patterning process, so that the source electrode, the drain electrode and the pixel electrode are all at the same electrode layer, and the source electrode, the drain electrode and the pixel electrode whose formation needs two patterning processes in the existing method, is simplified to one time patterning process, so it reduces the thickness of the thin film transistor driving backplane, simplifies the manufacturing step, and saves the manufacturing cost.

First claim

What is claimed is:

1. A manufacturing method of a thin film transistor driving backplane, the method comprising:
manufacturing a backplane base provided with a plurality of active device structures;
disposing an electrode layer on the backplane base;
manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process, wherein the source electrode, the drain electrode and the pixel electrode are located in a same layer; and
sequentially forming a pixel definition layer and a spacer pillar on a layer whereat the source electrode, the drain electrode and the pixel electrode located.

2. The manufacturing method of claim 1 , wherein a material of the electrode layer is one of metal material and oxide transparent electrode material.

3. The manufacturing method of claim 1 , wherein manufacturing the backplane base comprises the following steps:
disposing a semiconductor layer on a base substrate;
fabricating the semiconductor layer into an active channel by a mask and photolithography process;
disposing a gate insulation layer on the active channel;
disposing a gate layer on the gate insulation layer;
fabricating the gate layer into a gate electrode by mask and photolithography process;
disposing an isolation protection layer on the gate electrode;
disposing an interlayer dielectric layer on the isolation protection layer; and
forming a contact hole in the isolation protection layer, the interlayer dielectric layer, and the gate insulation layer by a mask and photolithography process.

4. The manufacturing method of claim 1 , wherein a material of the electrode layer is one of metal material and oxide transparent electrode material.

5. The manufacturing method of claim 4 , wherein manufacturing the backplane base comprises the following steps:
disposing a semiconductor layer on a base substrate;
fabricating the semiconductor layer into an active channel by a mask and photolithography process;
disposing a gate insulation layer on the active channel;
disposing a gate layer on the gate insulation layer;
fabricating the gate layer into a gate electrode by mask and photolithography process;
disposing an isolation protection layer on the gate electrode;
disposing an interlayer dielectric layer on the isolation protection layer; and
forming a contact hole in the isolation protection layer, the interlayer dielectric layer, and the gate insulation layer by a mask and photolithography process.

6. The manufacturing method of claim 1 , wherein manufacturing the backplane base comprises the following steps:
disposing a semiconductor layer on a base substrate;
fabricating the semiconductor layer into an active channel by a mask and photolithography process;
disposing a gate insulation layer on the active channel;
disposing a gate layer on the gate insulation layer;
fabricating the gate layer into a gate electrode by mask and photolithography process;
disposing an isolation protection layer on the gate electrode;
disposing an interlayer dielectric layer on the isolation protection layer; and
forming a contact hole in the isolation protection layer, the interlayer dielectric layer, and the gate insulation layer by a mask and photolithography process.

7. The manufacturing method of claim 6 , wherein disposing the isolation protection layer on the gate electrode comprises:
disposing a layer of metal thin film on the gate electrode; and
oxidizing the metal thin film as the isolation protection layer by an oxidizing process.

8. The manufacturing method of claim 6 , wherein disposing the semiconductor layer on the base substrate comprises:
disposing a buffer layer on the base substrate;
disposing an amorphous silicon thin film on the buffer layer;
performing a dehydrogenation treatment on the amorphous silicon thin film; and
performing an excimer laser annealing treatment on the amorphous silicon thin film, to convert the amorphous silicon thin film into a poly silicon thin film, wherein the poly silicon thin film is the semiconductor layer.

9. The manufacturing method of claim 6 , wherein the active channel comprises a source contact region, a drain contact region and a channel connecting region disposed between the source contact region and the drain contact region,
wherein fabricating the semiconductor layer into the active channel by the mask and photolithography process comprise:
performing dopant injection on the active channel by an ion injection process, wherein during the injection, dopants are respectively injected into the source contact region and the drain contact region by using the gate electrode as the mask; and
activating the dopant by an activating process.

10. A thin film transistor driving backplane, which is manufactured by the manufacturing method of claim 1 , wherein the thin film transistor driving backplane comprises a backplane base provided with a plurality of active device structures, and a source electrode, a drain electrode, and a pixel electrode disposed on the backplane base, the pixel electrode being disposed integrally with the drain electrode and the source electrode, the drain electrode, and the pixel electrode located in a same layer.

11. The thin film transistor driving backplane of claim 10 , wherein the backplane base comprises a base substrate, and a plurality of active channels, a gate insulation layer, a plurality of gate electrodes, an isolation protection layer and an interlayer dielectric layer are sequentially disposed on the base substrate, and a plurality of contact holes are formed in the isolation protection layer, the interlayer dielectric layer and the gate insulation layer to electrically connect the source electrode and the drain electrode to the active channel, respectively.

12. A display panel, comprising the thin film transistor backplane of claim 10 .

13. The display panel of claim 12 , wherein the backplane base comprises a base substrate, and a plurality of active channels, a gate insulation layer, a plurality of gate electrodes, an isolation protection layer and an interlayer dielectric layer are sequentially disposed on the base substrate, and a plurality of contact holes are formed in the isolation protection layer, the interlayer dielectric layer and the gate insulation layer to electrically connect the source electrode and the drain electrode to the active channel, respectively.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zuqiang
• Liu Chien Hung

Classifications

• H01L27/124

  Electricity · mapped topic

• H01L45/1691

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H01L27/1288

  Electricity · mapped topic

• H01L28/88

  Electricity · mapped topic