Array substrate and manufacturing method thereof, display device

US9543331B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9543331-B2
Application numberUS-201414435877-A
CountryUS
Kind codeB2
Filing dateSep 20, 2014
Priority dateMay 13, 2014
Publication dateJan 10, 2017
Grant dateJan 10, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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An array substrate and manufacturing method thereof, and a display device are capable of preventing light reflection from a drain electrode, and guaranteeing the display effect of the display device. The array substrate includes a drain electrode of a thin film transistor unit, an insulating layer and a pixel electrode. The insulating layer is located between the drain electrode and the pixel electrode, and has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole. A surface of the pixel electrode at the via hole is a rough face.

First claim

Opening claim text (preview).

The invention claimed is: 1. An array substrate, comprising: a base substrate; a drain electrode of a thin film transistor unit, an insulating layer and a pixel electrode on the base substrate, wherein, the insulating layer is located between the drain electrode and the pixel electrode, the insulating layer has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole, a surface of the pixel electrode at the via hole is a rough face, wherein an orthographic projection of the drain electrode of the thin film transistor on the base substrate falls completely within a scope of orthographic projection of the rough face of the pixel electrode. 2. The array substrate according to claim 1 , wherein, the surface of the pixel electrode at the via hole is subjected to a plasma treatment. 3. The array substrate according to claim 2 , wherein, the plasma includes hydrogen plasma or silane plasma. 4. The array substrate according to claim 1 , wherein, the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide. 5. The array substrate according to claim 4 , wherein, the rough face of the pixel electrode includes metal indium in big particles. 6. A display device, comprising the array substrate according to claim 1 . 7. A manufacturing method of an array substrate, comprising: forming a drain electrode of a thin film transistor unit, an insulating layer and a pixel electrode on a base substrate, wherein, the insulating layer is located between the drain electrode and the pixel electrode, and has a via hole formed therein, and the drain electrode and the pixel electrode are connected through the via hole; treating a surface of the pixel electrode at the via hole to be a rough face, wherein an orthographic projection of the drain electrode of the thin film transistor on the base substrate falls completely within a scope of orthographic projection of the rough face of the pixel electrode. 8. The manufacturing method of the array substrate according to claim 7 , wherein, treating the surface of the pixel electrode at the via hole to be the rough face includes: treating the pixel electrode at the via hole with plasma, so that the surface of the pixel electrode at the via hole is the rough face. 9. The manufacturing method of the array substrate according to claim 8 , wherein, the plasma includes hydrogen plasma or silane plasma. 10. The manufacturing method of the array substrate according to claim 7 , wherein, the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide. 11. The manufacturing method of the array substrate according to claim 10 , wherein, the rough face of the pixel electrode includes metal indium in big particles. 12. The array substrate according to claim 2 , wherein, the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide. 13. The array substrate according to claim 3 , wherein, the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide. 14. The display device according to claim 6 , wherein, the surface of the pixel electrode at the via hole is subjected to a plasma treatment. 15. The display device according to claim 14 , wherein, the plasma includes hydrogen plasma or silane plasma. 16. The display device according to claim 6 , wherein, the pixel electrode is made of a transparent conductive thin film of an indium oxide based metal oxide. 17. The display device according to claim 16 , wherein, the rough face of the pixel electrode includes metal indium in big particles.

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What does patent US9543331B2 cover?
An array substrate and manufacturing method thereof, and a display device are capable of preventing light reflection from a drain electrode, and guaranteeing the display effect of the display device. The array substrate includes a drain electrode of a thin film transistor unit, an insulating layer and a pixel electrode. The insulating layer is located between the drain electrode and the pixel e…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/124. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).