Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9543307-B2
Application number	US-201514792114-A
Country	US
Kind code	B2
Filing date	Jul 6, 2015
Priority date	Nov 6, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

First claim

What is claimed is:

1. A method of manufacturing a vertical memory device, the method comprising:
providing a substrate including a cell array region and a peripheral circuit region;
forming a mold structure on the cell array region of the substrate, the mold structure having a first portion and a second portion integrally connected to the first portion, the second portion having a plurality of steps;
forming an insulating layer on the second portion of the mold structure;
forming a common source line opening, the common source line opening extending through the first portion and the second portion of the mold structure in a first direction, the first direction being perpendicular to an upper surface of the substrate;
forming cell gate line contact holes extending-through the insulating layer in the first direction to the plurality of steps, each step of the plurality of steps being exposed by at least one of the cell gate line contact holes; and
simultaneously forming a first contact plug in the common source line opening and second contact plugs in the cell gate line contact holes,
wherein an upper surface of the first contact plug is substantially coplanar with upper surfaces of the second contact plugs.

2. The method of claim 1 , wherein
the insulating layer has an upper surface that is substantially coplanar with an upper surface of the mold structure.

3. The method of claim 1 , wherein the mold structure includes a plurality of interlayer insulating films and a plurality of sacrificial films that are alternately stacked on the cell array region of the substrate along the first direction.

4. The method of claim 3 , wherein
forming the common source line opening includes forming a plurality of interlayer insulating film patterns and a plurality of sacrificial film patterns from the plurality of interlayer insulating films and the plurality of sacrificial films, respectively, and
the method further includes
removing the plurality of sacrificial film patterns to form one or more space regions between the interlayer insulating film patterns; and
forming a plurality of cell gate lines in the space regions.

5. The method of claim 4 , wherein the cell gate line contact holes extend through the insulating layer and the plurality of interlayer insulating film patterns on the cell array region of the substrate, the cell gate line contact holes partially exposing the plurality of cell gate lines.

6. The method of claim 5 , further comprising:
forming a first hard mask pattern on the substrate such that a first void is formed in the common source line opening;
forming the cell gate line contact holes based on using the first hard mask pattern as a first etching mask; and
removing the first hard mask pattern from the substrate.

7. The method of claim 4 , further comprising:
forming a separation film pattern on a sidewall of the common source line opening to cover one or more sidewalls of the plurality of cell gate lines.

8. The method of claim 7 , further comprising:
forming an impurity region on an exposed upper portion of the substrate, the upper portion of the substrate exposed by the common source line opening,
wherein forming the impurity region includes
implementing a primary impurity implantation process subsequent to forming the common source line opening, and
implementing a second impurity implantation process subsequently to forming the separation film pattern.

9. The method of claim 4 , further comprising:
forming a plurality of channels extending through the mold structure in the first direction,
wherein the plurality of cell gate lines surround the plurality of channels.

10. The method of claim 9 , wherein the common source line opening extends between the channels.

11. The method of claim 9 , further comprising:
forming a dielectric film between the plurality of channels and the plurality of cell gate lines.

12. A method of manufacturing a vertical memory device, the method comprising:
providing a substrate, the substrate including a cell array region and a peripheral circuit region;
forming a mold structure on the cell array region of the substrate such that the peripheral circuit region of the substrate remains exposed, the mold structure having a first portion and a second portion integrally connected to the first portion, the second portion having a plurality of steps;
forming an insulating layer on the second portion of the mold structure and on the peripheral circuit region of the substrate;
forming a common source line opening, the common source line opening extending through the first portion and the second portion of the mold structure in a first direction, the first direction being perpendicular to an upper surface of the substrate;
forming a plurality of cell gate line contact holes extending through the insulating layer in the first direction to the plurality of steps, each of the plurality of steps being exposed by at least one of the cell gate line contact holes;
forming a peripheral circuit contact hole extending through the insulating layer on the peripheral circuit region, the peripheral circuit contact hole extending in the first direction; and
simultaneously forming a common source line contact plug in the common source line opening, a plurality of cell gate line contact plugs in the plurality of cell gate line contact holes, and a peripheral circuit contact plug in the peripheral circuit contact hole,
wherein an upper surface of the first contact plug is substantially coplanar with upper surfaces of the cell gate line contact plugs and upper surface of the peripheral circuit contact plug.

13. The method of claim 12 , wherein the common source line opening extends in a second direction, the second direction being perpendicular to the first direction.

14. The method of claim 12 , wherein the upper surface of the common source line contact plug, the upper surface of each cell gate line contact plug, and the upper surface of the peripheral circuit contact plug are substantially coplanar with at least one of an upper surface of the mold structure and an upper surface of the insulating layer.

15. The method of claim 12 , wherein,
the mold structure includes a plurality of interlayer insulating films and a plurality of sacrificial films that are alternately stacked on the cell array region of the substrate along the first direction,
forming the common source line opening includes forming a plurality of interlayer insulating film patterns and a plurality of sacrificial film patterns from the plurality of interlayer insulating films and the plurality of sacrificial films, respectively, and
the method further includes,
removing the plurality of sacrificial film patterns to form space regions between the interlayer insulating film patterns; and
forming a plurality of cell gate lines in the space regions.

16. The method of claim 15 , wherein the plurality of cell gate line contact holes extend through the insulating layer and the plurality of interlayer insulating film patterns on the cell array region of the substrate, the plurality of cell gate line contact holes partially exposing the plurality of cell gate lines.

17. The method of claim 16 , further comprising:
forming a first hard mask pattern on the substrate such that a first void is formed in the common source line opening;
forming the plurality of cell gate line contact holes based on using the first hard mask pattern as a first etching mask;
removing the first hard mask pattern from the substrate;
forming a second hard mask pattern on the sub

Assignees

• Kim Ha-Na
• Jang Dae-Hyun
• Oh Jung-Ik
• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Na
• Jang Dae-Hyun
• Oh Jung-Ik

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L21/4846

  Electricity · mapped topic