Semiconductor apparatus and method for producing the same

Patent metadata

Field	Value
Publication number	US-9543252-B2
Application number	US-201214412778-A
Country	US
Kind code	B2
Filing date	Jul 11, 2012
Priority date	Jul 11, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A plurality of semiconductor devices provided on a silicon carbide substrate are provided with electrode layers, respectively. The silicon carbide substrate is cut at a region of an exposed surface of the silicon carbide substrate that separates the electrode layers to individually separate the semiconductor devices. A stress relaxation resin is applied to each individually separated semiconductor device to cover the exposed surface at a peripheral end portion of that surface of the semiconductor device which has the electrode layer thereon. A semiconductor apparatus can thus be obtained that also allows a semiconductor device with a silicon carbide or similar compound semiconductor substrate to adhere to a sealant resin via large adhesive strength and thus allows the sealant resin to be less crackable, less peelable and the like by thermal stress caused in operation.

First claim

The invention claimed is:

1. A method for producing a semiconductor apparatus, comprising the steps of:
providing electrode layers to a plurality of semiconductor devices, respectively, provided on a silicon carbide substrate;
cutting said silicon carbide substrate at a region of an exposed surface of said silicon carbide substrate without an insulating layer that separates said electrode layers on a single plane to individually separate said semiconductor devices;
applying a stress relaxation resin to each of said individually separated semiconductor devices to cover only peripheral end portions of a surface of said semiconductor device which has said electrode layer thereon and to contact said exposed surface of said silicon carbide substrate without said insulating layer;
connecting a lead member to said electrode layer; and
applying a sealant resin to seal said semiconductor device covered with said stress relaxation resin.

2. The method for producing a semiconductor apparatus according to claim 1 , wherein:
said stress relaxation resin contains one of polyimide resin and polyimide-amide resin as a major component; and
said sealant resin contains epoxy resin as a major component.

3. The method for producing a semiconductor apparatus according to claim 2 , wherein the step of applying a stress relaxation resin includes the steps of:
applying said stress relaxation resin in a form of a liquid to coat said semiconductor device therewith; and
heating and thus setting said stress relaxation resin at a temperature equal to or lower than 250° C.

4. The method for producing a semiconductor apparatus according to claim 1 , wherein said stress relaxation resin has a modulus of elasticity equal to or smaller than 8 GPa.

5. The method for producing a semiconductor apparatus according to claim 4 , wherein said stress relaxation resin has a breaking elongation rate equal to or larger than 40%.

6. The method for producing a semiconductor apparatus according to claim 1 , further comprising the step of applying an insulating resin to cover a peripheral portion of each said electrode layer before the step of cutting, wherein the step of cutting is performed to cut said silicon carbide substrate at a dicing region that separates said portion covered with said insulating resin from another said portion covered with said insulating resin.

7. The method for producing a semiconductor apparatus according to claim 6 , wherein said stress relaxation resin and said insulating resin contain identical types, respectively, of one of polyimide resin and polyimide-amide resin as a major component.

8. The method for producing a semiconductor apparatus according to claim 1 , wherein said stress relaxation resin extends from a peripheral end portion of said semiconductor device uninterruptedly to also cover a section of said silicon carbide substrate.

9. A semiconductor apparatus comprising:
a semiconductor device including a silicon carbide substrate having an exposed surface without an insulating layer;
a lead member connected to an electrode layer of said semiconductor device;
an electrically conductive member in a form of a plate containing copper as a major component and bonded to a first surface of said semiconductor device opposite a second surface of said semiconductor device having said electrode thereon; and
a sealant resin containing epoxy resin as a major component and sealing said semiconductor device, said lead member, and said electrically conductive member,
said semiconductor device having a covering layer of one of polyimide resin and polyamide-imide resin that covers only peripheral end portions of said second surface having said electrode thereon, and said covering layer being in contact with said exposed surface of said silicon carbide substrate without said insulating layer, and
said covering layer being in contact with said sealant resin.

10. The semiconductor apparatus according to claim 9 , wherein said sealant resin has a coefficient of linear expansion in a range of 10-17 ppm.

11. The semiconductor apparatus according to claim 9 , wherein said electrically conductive member is in contact with said sealant resin.

12. The method for producing a semiconductor apparatus according to claim 1 , further comprising:
applying the stress relaxation resin to cover said exposed surface at only peripheral end portions so that a central portion of said exposed surface remains uncovered by said stress relaxation resin; and
applying the sealant resin to be in direct contact with the central portion of said exposed surface.

13. The method for producing a semiconductor apparatus according to claim 1 , further comprising:
applying an insulating resin to cover a peripheral portion of each of said electrode layers,
wherein the applying said stress relaxation resin further includes applying said stress relaxation resin to cover a peripheral portion of said insulating resin.

14. The semiconductor apparatus according to claim 9 , further comprising:
an insulating layer covering a peripheral portion of each of said electrode layers.

Assignees

• Terai Mamoru
• Idaka Shiori
• Yamamoto Kei
• Nakaki Yoshiyuki
• Mitsubishi Electric Corp

Inventors

• Terai Mamoru
• Idaka Shiori
• Yamamoto Kei
• Nakaki Yoshiyuki

Classifications

• H10W72/534

  being rectangular · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title