Methods of fabricating semiconductor devices using nanowires

Patent metadata

Field	Value
Publication number	US-9543196-B2
Application number	US-201514674332-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Aug 27, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming guide patterns exposing base patterns;
forming first nanowires on the base patterns by performing a first nanowire growth process;
forming a first molding insulating layer between the first nanowires;
forming holes exposing surfaces of the base patterns by removing the first nanowires; and
forming first electrodes comprising a conductive material in the holes.

2. The method of claim 1 , wherein the base patterns include at least one of poly-crystalline silicon, a metal, or a metal compound.

3. The method of claim 1 , wherein the guide patterns include silicon nitride.

4. The method of claim 1 , wherein the first nanowires include zinc oxide.

5. The method of claim 1 , wherein the first molding insulating layer includes silicon oxide.

6. The method of claim 1 , further comprising forming barrier patterns on the surfaces of the base patterns exposed in the holes.

7. The method of claim 6 , wherein the barrier patterns include a metal silicide or a metal compound.

8. The method of claim 1 , further comprising:
removing the first molding insulating layer to expose surfaces of the first electrodes;
forming a dielectric layer on the exposed surfaces of the first electrodes; and
forming a second electrode on the dielectric layer.

9. The method of claim 8 , wherein the dielectric layer is formed on surfaces of the guide patterns.

10. The method of claim 1 , further comprising:
recessing upper surfaces of the first nanowires to be lower than an upper surface of the first molding insulating layer;
forming second nanowires on the first nanowires by performing a second nanowire growth process using the first molding insulating layer as a guide; and
forming a second molding insulating layer between the second nanowires on the first molding insulating layer.

11. A method of forming a semiconductor device, the method comprising:
forming guide patterns exposing base patterns;
forming first nanowires on the base patterns;
forming a first molding insulating layer between the first nanowires;
recessing an upper surface of the first molding insulating layer to be lower than upper surfaces of the first nanowires;
forming a first supporter exposing the upper surfaces of the first nanowires and surrounding side surfaces of the first nanowires on the first molding insulating layer;
forming storage holes exposing surfaces of the base patterns by removing the first nanowires; and
forming first electrodes comprising a conductive material in the storage holes.

12. The method of claim 11 , further comprising:
recessing the upper surfaces of the first nanowires to be lower than an upper surface of the first supporter; and
forming second nanowires on the first nanowires using the first supporter as a guide.

13. The method of claim 12 , further comprising:
forming a second molding insulating layer between the second nanowires on the first supporter;
recessing an upper surface of the second molding insulating layer to be lower than upper surfaces of the second nanowires; and
forming a second supporter surrounding side surfaces of the second nanowires on the second molding insulating layer.

14. The method of claim 13 , further comprising:
forming an upper hole exposing a portion of the upper surface of the second molding insulating layer by patterning the second supporter; and
removing the second molding insulating layer through the upper hole.

15. The method of claim 14 , further comprising:
forming a lower hole exposing a portion of the upper surface of the first molding insulating layer by patterning the first supporter; and
removing the first molding insulating layer through the lower hole.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Hyun
• Im Dong-Hyun
• Lee Soon-Gun
• Lee Jong-Myeong
• Lim Han-Jin

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/279

  Vapour-liquid-solid growth · CPC title

• H10P14/274

  using seed materials · CPC title

• H10W20/0554

  of nanotubes or nanowires · CPC title