Defects annealing and impurities activation in semiconductors at thermodynamically non-stable conditions

Patent metadata

Field	Value
Publication number	US-9543168-B2
Application number	US-201615015381-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Feb 6, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond.

First claim

What is claimed is:

1. A process for annealing a semiconductor material without the material decomposing, the process including the steps of:
(1) capping a semiconductor sample with a material that is thermodynamically stable at maximum annealing temperature;
(2) positioning the capped semiconductor sample inside an enclosure;
(3) charging the enclosure with one of an inert gas, nitrogen, hydrogen, and mixtures thereof at an applied gas pressure above one atmosphere; and
(4) subjecting the capped semiconductor sample to a temperature T conv1 lower than temperature T S for a predetermined time period t conv1 , T S being a temperature above which the semiconductor sample becomes thermodynamically unstable at the applied gas pressure and t conv1 being at least several minutes or longer;
(5) at the end of t cov1 , subjecting the capped semiconductor sample to a plurality of heating and cooling cycles, each heating and cooling cycle including
(a) rapidly heating the sample for a duration of several seconds from a temperature Ts 1 tart to a predetermined temperature T max , Tstart being lower than T S and T max being higher than T S ;
(b) rapidly cooling the sample to a temperature T end for a duration of several seconds, T end being just lower than T S ; and
(c) holding the sample at the temperature range between Tstart and T end for a predetermined time period t hold , t hold being from several seconds up to several minutes;
wherein during each heating and cooling cycle the sample is exposed to temperatures within a predetermined temperature range between T S and T max for a predetermined time period t pulse , t pulse being less than a time t d at which the sample would start to decompose at the predetermined temperature range; and
wherein at the end of the plurality of heating and cooling cycles, the sample has been heated to temperatures within the predetermined temperature range between T S and T max for a total cumulative time of all cycles t sum greater than t d , without the sample decomposing; and

(6) following the last of the plurality of heating and cooling cycles, subjecting the capped semiconductor sample to a temperature T conv2 for a predetermined time period t conv2 , T conv2 being lower than T S and t conv2 being at least several minutes or longer;
wherein any one or more of T conv1 , Tstart, T end and T conv2 can be equal.

2. The process according to claim 1 , wherein the semiconductor material is SiC.

3. The process according to claim 1 , wherein the semiconductor material is diamond.

4. A product of the process of claim 1 .

5. The process according to claim 1 , wherein the semiconductor material is a III-nitride material.

6. The process according to claim 5 , wherein the III-nitride material is GaN.

7. The process according to claim 6 , wherein the cap is formed from a nitride material.

8. The process according to claim 7 , wherein the applied gas pressure is about 20 bar.

9. The process according to claim 8 , wherein the gas is nitrogen.

10. The process according to claim 7 , wherein the cap is AlN.

11. The process according to claim 10 , wherein the AlN cap is applied by means of MOCVD.

12. The process according to claim 10 , wherein the AlN cap is applied by means of sputtering.

13. The process according to claim 10 , wherein the AlN cap is composed of two or more layers of AlN applied by means of MOCVD and sputtering.

14. A process for annealing a semiconductor material without the material decomposing, the process including the steps of:
(1) capping a semiconductor sample with a material that is thermodynamically stable at an annealing temperature;
(2) implanting the sample with a plurality of dopant ions to form a doped capped semiconductor sample;
(3) positioning the doped capped semiconductor sample inside an enclosure;
(4) charging the enclosure with one of an inert gas, nitrogen, hydrogen, and mixtures thereof at an applied gas pressure above one atmosphere; and
(5) subjecting the doped capped sample to a temperature T conv1 lower than temperature T S for a predetermined time period t conv1 , T S being a temperature above which the doped capped semiconductor sample becomes thermodynamically unstable at the applied gas pressure and t conv1 being at least several minutes or longer;
(6) at the end of t conv1 , subjecting the doped capped semiconductor sample to a plurality of heating and cooling cycles, each heating and cooling cycle including
(a) rapidly heating the sample for a duration of several seconds from a temperature Tstart to a predetermined temperature T max , Tstart being lower than T S and T max being higher than T S ;
(b) rapidly cooling the sample to a temperature T end for a duration of several seconds, T end being just lower than T S ; and
(c) holding the sample at the temperature range between Tstart and T end for a predetermined time period t hold , t hold being from several seconds up to several minutes;
wherein during each heating and cooling cycle the sample is exposed to temperatures within a predetermined temperature range between T S and T max for a predetermined time period t pulse , t pulse being less than a time t d at which the sample would start to decompose at the predetermined temperature range; and
wherein at the end of the plurality of heating and cooling cycles, the sample has been heated to temperatures within the predetermined temperature range between T S and T max for a total cumulative time of all cycles t sum greater than t d , without the sample decomposing; and

(7) following the last of the plurality of heating and cooling cycles, subjecting the doped capped semiconductor sample to a temperature T conv2 for a predetermined time period t conv2 , T conv2 being lower than T S and t conv2 being at least several minutes or longer;
wherein any one or more of T conv1 , Tstart, T end and T conv2 can be equal.

15. The process according to claim 14 , wherein the cap is applied after implantation of the dopant ions.

16. The process according to claim 14 , wherein the semiconductor material is SiC.

17. The process according to claim 14 , wherein the semiconductor material is diamond.

18. A product of the process of claim 14 .

19. The process according to claim 14 , wherein semiconductor material is a III-nitride material.

20. The process according to claim 19 , wherein the III-nitride material is GaN.

21. The process according to claim 20 , wherein the applied gas pressure is about 20 bar.

22. The process according to claim 21 , wherein the gas is nitrogen.

23. The process according to claim 20 , wherein the GaN sample is implanted with Mg ions.

24. The process according to claim 23 , wherein after annealing, the GaN sample implanted with Mg ions shows uniform high p-type conductivity with sheet resistance RSH below 1 Ω·cm.

25. The process according to claim 23 , wherein GaN sample implanted with Mg ions has a structure of vertical p-i-n diode shows p-i-n rectification characteristics.

26. The process according to claim 20 , wherein the cap is formed from a nitride material.

27. The process according to claim 26 , wherein the cap is AlN.

28. The process according to claim 27 , wherein the AlN cap is applied by means of MOCVD.

29. The process according to claim 27 , wherein the AlN cap is applied by means of sp

Assignees

• Us Navy

Inventors

• Feigelson Boris N
• Greenlee Jordan
• Anderson Travis J
• Kub Francis J

Classifications

• H10P32/174

  being Group III-V material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title