Method of forming minute patterns and method of manufacturing a semiconductor device using the same

Patent metadata

Field	Value
Publication number	US-9543155-B2
Application number	US-201514975932-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Jan 23, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
sequentially forming a first etch target layer and a first mask layer on a substrate, the substrate having a first region and a second region therein;
forming a plurality of sacrificial patterns on the first mask layer in a second direction, each of the sacrificial patterns extending in a first direction crossing the second direction;
forming spacers on sidewalls of each of the sacrificial patterns;
removing the sacrificial patterns;
etching the first mask layer using the spacers as an etching mask to form a plurality of first masks;
forming second masks on sidewalls of each of the first masks in the second direction in the second region to define a plurality of third masks, each of the third masks including each of the first masks and the second masks on the sidewalls thereof; and
etching the first etch target layer using the first masks and the third masks as an etching mask to form a plurality of first patterns and a plurality of second patterns in the first region and the second region, respectively, each of the first patterns having a first width in the second direction, and each of the second patterns having a second width, the second width being greater than the first width in the second direction.

2. The method of claim 1 , wherein the forming second masks on sidewalls of each of the first masks in the second direction in the second region, includes:
forming a second mask layer on the first masks and the first etch target layer;
removing a portion of the second mask layer to expose the first masks and a first portion of a top surface of the first etch target layer in the first region, while a portion of the second mask layer in the second region remains; and
removing a portion of the second mask layer on a second portion of a top surface of the first etch target layer in the second region.

3. The method of claim 2 , wherein the removing a portion of the second mask layer in the first region, while a portion of the second mask layer in the second region remains, includes:
forming a first photoresist pattern on the second mask layer to cover the second region; and
performing an etching process using the first photoresist pattern as an etching mask to remove the portion of the second mask layer in the first region.

4. The method of claim 2 , further comprising:
before forming the second mask layer on the first masks and the first etch target layer, removing the spacers.

5. The method of claim 2 , wherein the removing a portion of the second mask layer on a second portion of a top surface of the first etch target layer in the second region further includes removing a portion of the second mask layer on top surfaces of the first masks in the second region to expose the second portion of the top surface of the first etch target layer and the top surfaces of the first masks in the second region.

6. The method of claim 1 , further comprising, prior to the sequentially forming a first etch target layer and a first mask layer:
forming a second etch target layer on the substrate.

7. The method of claim 6 , wherein the first etch target layer includes a material having an etch selectivity with respect to the first masks, the second masks, and the second etch target layer.

8. The method of claim 6 , further comprising, after the etching the first etch target layer using the first masks and the third masks as an etching mask to form a plurality of first patterns and a plurality of second patterns:
etching the second etch target layer using the first patterns and the second patterns as an etching mask to form a plurality of third patterns and a plurality of fourth patterns in the first region and the second region, respectively, each of the third patterns having the first width in the second direction, and each of the fourth patterns having the second width in the second direction.

9. The method of claim 8 , further comprising, prior to the forming a second etch target layer on the substrate:
forming a third etch target layer on the substrate,
and further comprising, after the etching the second etch target layer using the first patterns and the second patterns as an etching mask to form a plurality of third patterns and a plurality of second patterns:
etching the third etch target layer using the third patterns and the fourth patterns as an etching mask to form a plurality of fifth patterns and a plurality of sixth patterns in the first region and the second region, respectively, each of the fifth patterns having the first width in the second direction, and each of the sixth patterns having the second width in the second direction.

10. The method of claim 1 , wherein the forming a plurality of sacrificial patterns on the first mask layer in a second direction includes:
forming a sacrificial layer on the first mask layer;
forming a second photoresist pattern on the sacrificial layer; and
etching the sacrificial layer using the second photoresist pattern as an etching mask.

11. The method of claim 10 , wherein the forming spacers on sidewalls of each of the sacrificial patterns includes:
forming a spacer layer on the first mask layer to cover the sacrificial patterns; and
anisotropically etching the spacer layer.

12. The method of claim 1 , wherein the first region is a logic region in which logic devices are formed, and the second region is a static random access memory (SRAM) region in which SRAM devices are formed.

13. A method of manufacturing a semiconductor device, the method comprising:
sequentially forming a gate layer, a hard mask layer, and an intermediate layer on a substrate, the substrate having first and second regions therein;
forming a plurality of first masks on the intermediate layer in a second direction, each of the first masks extending in a first direction crossing the second direction;
forming a second mask layer on the first masks and the intermediate layer;
removing a portion of the second mask layer in the first region;
removing portions of the second mask layer on top surfaces of the first masks and a top surface of the intermediate layer to form second masks on sidewalls of each of the first masks in the second region, the top surfaces of the first masks and the top surface of the intermediate layer being exposed, and each of the first masks and the second masks on the sidewalls of each of the first masks defining a third mask;
etching the intermediate layer using the first masks and the third masks as an etching mask to form a plurality of first patterns and a plurality of second patterns in the first region and the second region, respectively, each of the first patterns having a first width in the second direction, and each of the second patterns having a second width in the second direction, the second width being greater than the first width;
etching the hard mask layer using the first patterns and the second patterns as an etching mask to form a plurality of first hard masks and a plurality of second hard masks in the first region and the second region, respectively; and
etching the gate layer using the first hard masks and the second hard masks as an etching mask to form first gates and second gates in the first region and the second region, respectively.

14. The method of claim 13 , wherein the removing a portion of the second mask layer in the first region includes:
forming a first photoresist pattern on the second mask layer to cover the second region; and
performing a wet etching process using the first photoresist pattern as an etching mask to remove the portion of the

Assignees

• Lee Bok-Young
• Lee Yoo-Jung
• KHANG Dong-Hoon
• Kim Do-Hyoung
• Kim Cheol
• Lee In-Hee
• Han Ji-Eun
• Samsung Electronics Co Ltd

Inventors

• Lee Bok-Young
• Lee Yoo-Jung
• KHANG Dong-Hoon
• Kim Do-Hyoung
• Kim Cheol
• Lee In-Hee
• Han Ji-Eun

Classifications

• H10D64/01328 Primary

  by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L27/1104

  Electricity · mapped topic

• H01L27/1116

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic