Transformer, method for manufacturing transformer and chip

Patent metadata

Field	Value
Publication number	US-9543073-B2
Application number	US-201415036317-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	Dec 19, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A transformer, a method for manufacturing the transformer and a chip are provided. The method includes: a first primary tuning capacitor and/or a first secondary tuning capacitor are/is arranged in an area enclosed by a primary coil and a secondary coil, wherein the first primary tuning capacitor includes more than one second primary tuning capacitor, and the first secondary tuning capacitor includes more than one second secondary tuning capacitor; the more than one second primary tuning capacitor are connected in parallel, and the more than one second secondary tuning capacitor are connected in parallel; and the more than one second primary tuning capacitor and the at least one wire between the more than one second primary tuning capacitor, and/or the more than one second secondary tuning capacitor and the at least one wire between the more than one second secondary tuning capacitor form a partially-shielded network or part of the partially-shielded network.

First claim

What is claimed is:

1. A method for manufacturing a transformer, the transformer comprising a primary coil, a secondary coil, a first primary tuning capacitor and a first secondary tuning capacitor, and the method comprising:
arranging the first primary tuning capacitor and/or the first secondary tuning capacitor in an area enclosed by the primary coil and the secondary coil, the first primary tuning capacitor comprising more than one second primary tuning capacitor, and the first secondary tuning capacitor comprising more than one second secondary tuning capacitor;
connecting the more than one second primary tuning capacitor in parallel, and connecting the more than one second secondary tuning capacitor in parallel; and
forming a partially-shielded network or part of the partially-shielded network by the more than one second primary tuning capacitor and at least one wire between the more than one second primary tuning capacitor, and/or by the more than one second secondary tuning capacitor and at least one wire between the more than one second secondary tuning capacitor.

2. The method according to claim 1 , wherein arranging the first primary tuning capacitor and/or the first secondary tuning capacitor in an area enclosed by the primary coil and the secondary coil comprises:
arranging all or some of the more than one second primary tuning capacitor and/or all or some of the more than one second secondary tuning capacitor in a blank area enclosed by the primary coil and the secondary coil or under the blank area.

3. The method according to claim 1 , wherein the transformer comprises an on-chip passive transformer or an on-chip transformer-type balun.

4. The method according to claim 1 , wherein capacitances of the more than one second primary tuning capacitor are completely or incompletely the same;
and/or, capacitances of the more than one second secondary tuning capacitor are completely or incompletely the same.

5. The method according to claim 1 , further comprising:
winding the primary coil and the secondary coil mutually and symmetrically on a same substrate via a metal on a same layer, and adopting an upper-layer metal or a lower-layer metal for transition in a crossed part of metal wires.

6. A transformer, comprising: a primary coil, a secondary coil, a first primary tuning capacitor and a first secondary tuning capacitor, wherein the first primary tuning capacitor comprises more than one second primary tuning capacitor which are connected in parallel; and the first secondary tuning capacitor comprises more than one second secondary tuning capacitor which are connected in parallel;
the first primary tuning capacitor and/or the first secondary tuning capacitor are/is arranged in an area enclosed by the primary coil and the secondary coil; and the more than one second primary tuning capacitor and at least one wire between the more than one second primary tuning capacitor, and/or the more than one second secondary tuning capacitor and at least one wire between the more than one second secondary tuning capacitor form a partially-shielded network or part of a partially-shielded network.

7. The transformer according to claim 6 , wherein the primary coil and the secondary coil are mutually and symmetrically wound on a same substrate via a metal on a same layer, and an upper-layer metal or a lower-layer metal is adopted for transition in a crossed part of metal wires.

8. The transformer according to claim 6 , wherein all or some of the more than one second primary tuning capacitor and/or all or some of the more than one second primary tuning capacitor are arranged in a blank area enclosed by the primary coil and the secondary coil or under the blank area.

9. The transformer according to claim 6 , wherein capacitances of the more than one second primary tuning capacitor are completely or incompletely the same;
and/or, capacitances of the more than one second secondary tuning capacitor are completely or incompletely the same.

10. A chip, comprising a transformer comprising a primary coil, a secondary coil, a first primary tuning capacitor and a first secondary tuning capacitor, wherein the first primary tuning capacitor comprises more than one second primary tuning capacitor which are connected in parallel; and the first secondary tuning capacitor comprises more than one second secondary tuning capacitor which are connected in parallel;
the first primary tuning capacitor and/or the first secondary tuning capacitor are/is arranged in an area enclosed by the primary coil and the secondary coil; and the more than one second primary tuning capacitor and at least one wire between the more than one second primary tuning capacitor, and/or the more than one second secondary tuning capacitor and at least one wire between the more than one second secondary tuning capacitor form a partially-shielded network or part of a partially-shielded network.

11. The method according to claim 2 , further comprising:
winding the primary coil and the secondary coil mutually and symmetrically on a same substrate via a metal on a same layer, and adopting an upper-layer metal or a lower-layer metal for transition in a crossed part of metal wires.

12. The method according to claim 3 , further comprising:
winding the primary coil and the secondary coil mutually and symmetrically on a same substrate via a metal on a same layer, and adopting an upper-layer metal or a lower-layer metal for transition in a crossed part of metal wires.

13. The method according to claim 4 , further comprising:
winding the primary coil and the secondary coil mutually and symmetrically on a same substrate via a metal on a same layer, and adopting an upper-layer metal or a lower-layer metal for transition in a crossed part of metal wires.

14. The transformer according to claim 7 , wherein capacitances of the more than one second primary tuning capacitor are completely or incompletely the same;
and/or, capacitances of the more than one second secondary tuning capacitor are completely or incompletely the same.

15. The transformer according to claim 8 , wherein capacitances of the more than one second primary tuning capacitor are completely or incompletely the same;
and/or, capacitances of the more than one second secondary tuning capacitor are completely or incompletely the same.

16. The chip according to claim 10 , wherein the primary coil and the secondary coil are mutually and symmetrically wound on a same substrate via a metal on a same layer, and an upper-layer metal or a lower-layer metal is adopted for transition in a crossed part of metal wires.

17. The chip according to claim 10 , wherein all or some of the more than one second primary tuning capacitor and/or all or some of the more than one second primary tuning capacitor are arranged in a blank area enclosed by the primary coil and the secondary coil or under the blank area.

18. The chip according to claim 10 , wherein capacitances of the more than one second primary tuning capacitor are completely or incompletely the same;
and/or, capacitances of the more than one second secondary tuning capacitor are completely or incompletely the same.

19. The chip according to claim 16 , wherein capacitances of the more than one second primary tuning capacitor are completely or incompletely the same;
and/or, capacitances of the more than one second secondary tuning capacitor are completely or incompletely the same.

20. A chip according to claim 17 , wherein capacitances of the more than one second primary tuning

Assignees

• Zte Corp
• Sanechips Tech Co Ltd
• Sanechips Tech Co Ltd

Inventors

• Xie Haolv
• Wu Zhangbin

Classifications

• H01F27/40 Primary

  Structural association with built-in electric component, e.g. fuse · CPC title

• H01F41/06

  Coil winding · CPC title

• H03H7/0115

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H01F27/2823

  Wires (H01F27/2866 takes precedence) · CPC title

• H03H7/42

  Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns · CPC title