Error corrected pre-read for upper page write in a multi-level cell memory

Patent metadata

Field	Value
Publication number	US-9543019-B2
Application number	US-201213710913-A
Country	US
Kind code	B2
Filing date	Dec 11, 2012
Priority date	Dec 11, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.

First claim

What is claimed is:

1. A controller-based method to program a multi-level cell (MLC) memory, comprising:
receiving, in a controller, a write command from a host device, the write command comprising a program address and program data;
in response to the write command, mapping the program address to a targeted page of memory in the MLC memory; and
determining, in the controller, whether the targeted page of memory comprises an upper page and a lower page, and in response to a determination that targeted page of memory comprises an upper page and a lower page:
reading the lower page of the targeted page of memory to obtain lower page data, wherein the MLC memory has been programmed with the lower page data;
error correcting the lower page data to generate error corrected lower page data;
allocating one or more new pages of memory in the MLC memory;
calculating an error correcting code to be included with the error corrected lower page data;
determining whether the MLC memory would have to decrease a voltage threshold to program the error corrected lower page data, and in response to a determination that the MLC memory would have to decrease a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the one or more new pages of memory in the MLC memory; and
programming the MLC memory using the error corrected lower page data and the program data.

2. A method as claimed in claim 1 , wherein said error correcting is performed with a controller coupled to the MLC memory.

3. A method as claimed in claim 1 , wherein the MLC memory comprises NAND memory.

4. A method as claimed in claim 1 , wherein said programming comprises programming the lower page with the error corrected lower page data, and programming the upper page with the new upper page data.

5. An apparatus, comprising:
a memory including one or more multi-level cells (MLCs); and
a controller coupled to the memory, wherein the controller is configured to:
receive, in a controller, a write command from a host device, the write command including a program address and program data;
in response to the write command, map the program address to a targeted page of memory in the one or more MLCs; and
determine, in the controller, whether the targeted page of memory comprises an upper page and a lower page, and in response to a determination that targeted page of memory comprises an upper page and a lower page:
read the lower page of the targeted page of memory to obtain lower page data, wherein the one or more MLCs have been programmed with the lower page data;
error correct the lower page data;
allocate one or more new pages of memory in the one or more MLCs;
calculate an error correcting code to be included with the error corrected lower page data;
determine whether the one or more MLCs would have to increase a voltage threshold to program the error corrected lower page data, and in response to a determination that the one or more MLCs would have to increase a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the lower page of the targeted page of memory from which the lower page data was read; and
program the one or more MLCs using the error corrected lower page data and the program data.

6. An apparatus as claimed in claim 5 , wherein the memory comprises NAND memory.

7. An apparatus as claimed in claim 5 , wherein the controller is further configured to program the lower page with the error corrected lower page data, and program the upper page with the new upper page data.

8. A solid-state disk (SSD), comprising:
a bus interface;
one or more memory devices including one or more multi-level cells (MLCs); and
an SSD controller coupled to the one or more memory devices and to the bus interface, wherein the SSD controller is configured to:
receive, in a controller, a write command from a host device, the write command comprising a program address and program data;
in response to the write command, map the program address to a targeted page of memory in the one or more MLCs; and
determine whether the targeted page of memory comprises an upper page and a lower page, and in response to a determination that targeted page of memory comprises an upper page and a lower page:
read the lower page of the targeted page of memory to obtain lower page data, wherein the one or more MLCs have been programmed with the lower page data;
error correct the lower page data;
allocate one or more new pages of memory in the one or more MLCs;
calculate an error correcting code to be included with the error corrected lower page data;
determine whether the one or more MLCs would have to increase in a voltage threshold to program the error corrected lower page data, and in response to a determination that the one or more MLCs would have to increase a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the lower page of the targeted page of memory from which the lower page data was read; and
program the one or more MLCs using the error corrected lower page data and the program data.

9. A solid-state disk as claimed in claim 8 , wherein the one or more memory devices comprise one or more NAND memory devices.

10. A solid-state disk as claimed in claim 8 , wherein the SSD controller is further configured to program the lower page with the error corrected lower page data, and program the upper page with the new upper page data.

11. A solid-state disk as claimed in claim 8 , wherein the SSD controller is further configured to:
determine whether the one or more MLCs would have to decrease a voltage threshold to program the error corrected lower page data, and in response to a determination that the one or more MLCs would have to decrease a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the one or more new pages of memory in the one or more MLCs.

12. A method as claimed in claim 1 , further comprising:
determining whether the MLC memory would have to increase a voltage threshold to program the error corrected lower page data, and in response to a determination that the MLC memory would have to increase a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the lower page of the targeted page of memory from which the lower page data was read.

13. An apparatus as claimed in claim 5 , wherein the controller is further configured to:
determine whether the one or more MLCs would have to decrease a voltage threshold to program the error corrected lower page data, and in response to a determination that the one or more MLCs would have to decrease a voltage threshold to program the error corrected lower page data, programming the error corrected lower page data into the one or more new pages of memory in the one or more MLCs.

Assignees

• Intel Corp

Inventors

• Frickey Robert E
• Wakchaure Yogesh B
• Chao Iwen
• Guo Xin
• Gaewsky Kristopher H

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title