Organic light emitting diode display

US9542882B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9542882-B2
Application numberUS-201113305816-A
CountryUS
Kind codeB2
Filing dateNov 29, 2011
Priority dateJan 10, 2011
Publication dateJan 10, 2017
Grant dateJan 10, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An organic light emitting diode display includes: a panel; a data driver connected to a data line formed on the panel; a gate driver crossing the data line in an insulated manner and connected to gate lines formed on the panel; an input line for receiving clock signals from the outside; a first connecting line electrically connected to the input line to supply the clock signal to the gate driver; a second connecting line electrically connected to the input line; and a third connecting line extended from the second connecting line to electrically connect the second connecting line and the first connecting line.

First claim

Opening claim text (preview).

What is claimed is: 1. An organic light emitting diode display comprising: a panel comprising: a first electrode disposed on a first substrate; an organic emission layer disposed on the first electrode; and a second electrode disposed on the organic emission layer; a data driver connected to a data line formed in the panel; a gate driver connected to a gate line formed in the panel; an input line for receiving a clock signal from an outside element; a first connecting line directly electrically connected to the input line to supply the clock signal to the gate driver, the first connecting line overlapping with the second electrode; a second connecting line directly electrically connected to the input line, the second connecting line overlapping with none of the first and second electrodes; and a third connecting line electrically connecting the second connecting line to the first connecting line. 2. The organic light emitting diode display of claim 1 , wherein the gate line is formed with a gate transparent layer and a gate metal layer formed on the gate transparent layer, and the first electrode is formed on the same layer and with the same material as the gate transparent layer. 3. The organic light emitting diode display of claim 1 , wherein the first connecting line is formed on the same layer and with the same material as the data line. 4. The organic light emitting diode display of claim 1 , wherein the second connecting line is formed on the same layer and with the same material as the gate line. 5. The organic light emitting diode display of claim 4 , wherein the third connecting line is formed on the same layer and with the same material as the second connecting line. 6. The organic light emitting diode display of claim 1 , wherein the data line crosses the gate line, the panel further comprising: a first insulation layer provided between the gate line and the data line; and a second insulation layer provided on the data line and including an organic material, the second connecting line not overlapping with the second insulation layer.

Assignees

Inventors

Classifications

  • G09G3/3225Primary

    using an active matrix · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Details of drivers for scan electrodes · CPC title

  • comprising structures specially adapted for lowering the resistance · CPC title

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Frequently asked questions

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What does patent US9542882B2 cover?
An organic light emitting diode display includes: a panel; a data driver connected to a data line formed on the panel; a gate driver crossing the data line in an insulated manner and connected to gate lines formed on the panel; an input line for receiving clock signals from the outside; a first connecting line electrically connected to the input line to supply the clock signal to the gate drive…
Who is the assignee on this patent?
Kang Ki-Nyeng, Kim Na-Young, Lee Wang-Jo, and 3 more
What technology area does this patent fall under?
Primary CPC classification G09G3/3225. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).