Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system

Patent metadata

Field	Value
Publication number	US-9542351-B2
Application number	US-201214401162-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface. The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface. The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

First claim

The invention claimed is:

1. A memory controller, comprising:
a connection interface connected or connectable to a memory, the memory controller being arranged to read data from the memory via the connection interface;
a clock unit arranged to provide a data transfer clock signal having a first frequency, wherein the data transfer clock signal is provided to the memory via the connection interface, the data transfer clock signal being arranged for clocking a data transfer from the memory to the memory controller via the connection interface;
an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an oversampled calibration data pattern, the second frequency being larger than the first frequency, and wherein the calibration data pattern includes a predetermined sequence of bits;
wherein the memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

2. The memory controller of claim 1 , wherein the memory is a flash memory.

3. The memory controller of claim 1 , the memory controller being arranged to control the data transfer based on the oversampled calibration data pattern.

4. The memory controller of claim 1 , the memory controller being arranged to compare the oversampled calibration data pattern with one or more shifted patterns to determine the timing shift of the data transfer.

5. The memory controller of claim 1 , the memory controller being arranged to store a timing shift value indicative of a determined timing shift in a status register.

6. The memory controller of claim 1 , the connection interface comprising a Serial Peripheral Interface-based bus.

7. The memory controller of claim 1 , the connection interface comprising a plurality of data pins for reading data from the memory.

8. The memory controller of claim 7 , the oversampling circuit comprising an oversampling unit arranged to oversample data for each of the data pins.

9. The memory controller of claim 1 , the memory controller comprising an instruction set having at least one calibration instruction according to which the memory controller reads the calibration data pattern from the memory and oversamples the calibration data pattern to provide an oversampled calibration data pattern.

10. A method of calibrating data transfer of a memory system having a memory controller, and a memory connected to the memory controller via a connection interface, comprising:
reading, by the memory controller, a calibration data pattern from the memory via the connection interface, according to a data transfer clock signal having a first frequency provided by a clock unit of the memory controller, wherein the calibration data pattern includes a predetermined sequence of bits;
sampling, by an oversampling circuit of the memory controller, the calibration data pattern with a second frequency higher than the first frequency to provide an oversampled calibration data pattern; and
determining, by the memory controller, a timing shift of data transfer from the memory based on the oversampled calibration data pattern.

11. The method of claim 10 , further comprising comparing the oversampled calibration data pattern with one or more shifted patterns to determine the timing shift of the data transfer.

12. The method of claim 11 , further comprising controlling the data transfer based on the oversampled calibration data pattern.

13. The method of claim 11 , further comprising oversampling data for each a plurality of data pins of the connection interface via which the calibration data pattern is read.

14. The method of claim 11 , further comprising storing a timing shift value indicative of a determined timing shift in a status register.

15. A memory controller, comprising:
a connection interface connected or connectable to a flash memory, the memory controller being arranged to read data from the flash memory via the connection interface;
an instruction set storage device arranged to store an instruction set of the memory controller, the instruction set comprising one or more flexible instructions to access the flash memory,
wherein the memory controller, in response to at least one instruction of the flexible instruction set, is configured to:
read a calibration data pattern from the flash memory via the connection interface, according to a data transfer clock signal having a first frequency provided by a clock unit of the memory controller, wherein the calibration data pattern includes a predetermined sequence of bits;
sampling the calibration data pattern with a second frequency higher than the first frequency to provide an oversampled calibration data pattern; and
determining a timing shift of data transfer from the memory based on the oversampled calibration data pattern.

16. The memory controller of claim 15 , the flexible instruction set comprising flexible instructions which are adapted to an instruction set or timing of the flash memory.

17. The memory controller of claim 15 , wherein the memory controller, in response to the at least one instruction, is configured to compare the oversampled calibration data pattern with one or more shifted patterns to determine the timing shift of the data transfer.

18. A memory system, comprising:
a memory controller according to claim 1 ; and
a memory connected to the memory controller via the connection interface.

19. A computing system, comprising:
a memory controller as claimed in claim 1 and a microcontroller.

Assignees

• Beattie Derek
• Pandey Rakesh
• Sakalley Deboleena
• Nxp Usa Inc

Inventors

• Beattie Derek
• Pandey Rakesh
• Sakalley Deboleena

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title