Logical block addresses used for executing host commands

US9542122B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9542122-B2
Application numberUS-201414522160-A
CountryUS
Kind codeB2
Filing dateOct 23, 2014
Priority dateOct 23, 2014
Publication dateJan 10, 2017
Grant dateJan 10, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage compute device, comprising: a host interface that receives storage commands from a host that utilize logical block addresses; and a processing unit coupled to the host interface, the processing unit configured to: reserve a logical block address space used by the host interface, the logical block address space not being mapped to a physical address space of a non-volatile memory unit of the storage compute device; receive first data at a first portion of the logical block address space, the first data causing a computation to be performed by a computation engine of the storage compute device; and send second data to the host via a second portion of the logical block address space, the second data describing a result of the computation. 2. The storage compute device of claim 1 , wherein the first data comprises a command that causes the computation, the command written to a first starting address of the logical block address space. 3. The storage compute device of claim 2 , wherein the command references a compute object stored on the storage compute device, the compute object performing the computation. 4. The storage compute device of claim 2 , wherein the first data comprises metadata of one or more data objects used in the computation, the metadata written to a second starting address of the logical block address space. 5. The storage compute device of claim 4 , wherein data of one or more data objects are written to the second starting address. 6. The storage compute device of claim 4 , wherein data of the one or more data objects are written to a second logical block address space of the storage compute device used for legacy storage operations. 7. The storage compute device of claim 1 , wherein the first data is received using a legacy command set used for reading and writing data to the storage compute device. 8. A system comprising: a host processor; and at least one storage compute device comprising: a host interface coupled to the host processor via a data bus; a computation engine; a data storage section; and a controller coupled to the host interface, the data storage section, and the computation engine, the controller configured to: reserve a logical block address space used by the host interface, the logical block address space not being mapped to a physical address space of the data storage section; receive first data at a first portion of the logical block address space from the host processor, the first data causing a computation to be performed by the computation engine; and send second data to the host processor via a second portion of the logical block address space, the second data describing a result of the computation. 9. The system of claim 8 , wherein the first data comprises a command causing the computation and metadata of one or more data objects used in the computation, the command written to a first starting address of the logical block address space and the metadata written to a second starting address of the logical block address space. 10. The system of claim 9 , wherein the command references a compute object stored on the storage compute device, the compute object performing the computation. 11. The system of claim 7 , wherein the at least one storage compute device comprises a plurality of storage compute devices, and wherein the computation is distributed among the plurality of storage compute devices. 12. The system of claim 7 , further comprising a network interface capable of being coupled to a network node comprising a remote storage compute device, and wherein the host processor is configured to send, via the network, third data to a reserved logical block address space of the remote storage compute device, the third data causing a second computation to be performed by the remote storage compute device. 13. A processor-implemented method comprising: reserving a logical block address space of a storage compute device for use in executing commands from a host, the logical block address space not being mapped to a physical address space; receiving first data at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device; and sending second data to the host via a second portion of the logical block address space, the second data describing a result of the computation. 14. The method of claim 13 , wherein the first data comprises a command that causes the computation, the command written to a first starting address of the logical block address space. 15. The method of claim 14 , wherein the command references a compute object stored on the storage compute device, the compute object performing the computation. 16. The method of claim 14 , wherein the first data comprises metadata of one or more data objects used in the computation, the metadata written to a second starting address of the logical block address space. 17. The method of claim 16 , wherein data of one or more data objects are written to the second starting address. 18. The method of claim 16 , wherein data of the one or more data objects are written to a second logical block address space of the storage compute device used for legacy storage operations. 19. The method of claim 1 , wherein the first data is received using a legacy command set used for reading and writing data to the storage compute device. 20. The method of claim 19 , wherein a second logical address space of the storage compute device is used for legacy storage operations via the legacy command set.

Assignees

Inventors

Classifications

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • Improving or facilitating administration, e.g. storage management · CPC title

  • Management of blocks · CPC title

  • G06F3/0659Primary

    Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9542122B2 cover?
A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second po…
Who is the assignee on this patent?
Seagate Technology Llc
What technology area does this patent fall under?
Primary CPC classification G06F3/0659. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).