Power switch wafer test method

US9541599B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9541599-B2
Application numberUS-201214009347-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2012
Priority dateApr 4, 2011
Publication dateJan 10, 2017
Grant dateJan 10, 2017

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  1. Title

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  5. First independent claim

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Abstract

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A wafer test method of a power switch wherein a main IGBT and a current detecting IGBT that detects a current value of the main IGBT are integrally formed on the same semiconductor substrate is such that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT are energized simultaneously, thereby applying a constant current to a common collector terminal of the main IGBT and current detecting IGBT, and a current ratio (main current/detected current) between a main current of the main IGBT and a detected current of the current detecting IGBT is calculated from the current flowing through the current detecting IGBT, obtained from the voltage across the resistance means, and the constant current.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power switch wafer test method, being a wafer test method of a power switch having a main IGBT (Insulated Gate Bipolar Transistor) and a current detecting IGBT, of which a collector terminal and gate terminal are connected respectively to a collector terminal and gate terminal of the main IGBT and which detects a current value of the main IGBT, wherein the main IGBT and current detecting IGBT are integrally formed on a same semiconductor substrate, the power switch wafer test method comprising: providing resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, energizing the main IGBT and current detecting IGBT simultaneously, thereby applying a constant current to a common collector terminal of the main IGBT and current detecting IGBT, and calculating a current ratio between a main current of the main IGBT and a detected current of the current detecting IGBT from the current flowing through the current detecting IGBT, obtained from the voltage across the resistance means, and the constant current; wherein the resistance means is connected between a main IGBT test terminal and a current detecting IGBT test terminal of a wafer test probe card, the main IGBT test terminal and the current detecting IGBT test terminal corresponding to the emitter terminal of the main IGBT and an emitter terminal of the current detecting IGBT. 2. A power switch wafer test method, being a wafer test method of a power switch having a main IGBT and a current detecting IGBT, of which a collector terminal and gate terminal are connected respectively to a collector terminal and gate terminal of the main IGBT and which detects a current value of the main IGBT, wherein the main IGBT and current detecting IGBT are integrally formed on a same semiconductor substrate, the power switch wafer test method comprising: providing resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, energizing the main IGBT and current detecting IGBT simultaneously, detecting a total current of a main current of the main IGBT flowing from the emitter terminal of the main IGBT and a detected current of the current detecting IGBT, the detected current of the current detecting IGBT being detected from a voltage across the resistance means, and calculating a current ratio between the main current of the main IGBT and the detected current of the current detecting IGBT; wherein the resistance means is connected between a main IGBT test terminal and a current detecting IGBT test terminal of a wafer test probe card, the main IGBT test terminal and the current detecting IGBT test terminal corresponding to the emitter terminal of the main IGBT and an emitter terminal of the current detecting IGBT. 3. A method, comprising: using a testing device, applying a constant current to a common collector terminal of a main IGBT and a current-detecting IGBT; generating a voltage across a resistance provided in the testing device based on the constant current; determining a current flowing through the current-detecting IGBT based on the voltage and the resistance; and calculating a ratio of a main current of the main IGBT to a detected current of the current-detecting IGBT based on the constant current and the current determined to be flowing through the current-detecting IGBT; wherein the applying the constant current comprises using the testing device to energize the main IGBT and the current-detecting IGBT substantially simultaneously; and wherein the resistance is connected between a main IGBT test terminal and a current detecting IGBT test terminal of the testing device, the main IGBT test terminal and the current detecting IGBT test terminal corresponding to an emitter terminal of the main IGBT and an emitter terminal of the current-detecting IGBT. 4. The method of claim 3 , comprising generating the voltage across the resistance by dividing the constant current applied to the common collector terminal of the main IGBT and the current-detecting IGBT into a current flowing through the main IGBT and a current flowing through the resistance. 5. The method of claim 4 , wherein the calculating the ratio comprises determining a difference between the constant current and the current determined to be flowing through the current-detecting IGBT. 6. The method of claim 5 , wherein the calculating the ratio further comprises determining a value of the difference relative to the current determined to be flowing through the current-detecting IGBT.

Assignees

Inventors

Classifications

  • Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

  • Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

  • for testing bipolar transistors · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9541599B2 cover?
A wafer test method of a power switch wherein a main IGBT and a current detecting IGBT that detects a current value of the main IGBT are integrally formed on the same semiconductor substrate is such that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT ar…
Who is the assignee on this patent?
Sato Shigeki, Fuji Electric Co Ltd
What technology area does this patent fall under?
Primary CPC classification G01R31/2608. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).