Substrate structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9538647-B2
Application number	US-201414450297-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	May 26, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A substrate structure is provided. The substrate structure includes a substrate and a carrier. The substrate includes a first through hole, a first surface and a second surface opposite to the first surface. The first through hole penetrates the substrate for connecting the first surface and the second surface. The carrier includes a second through hole, a release layer, an insulating paste layer and a metal layer. The insulating paste layer is disposed between the release layer and the metal layer. The carrier is attached to the second surface with the release layer thereof. The second through hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole.

First claim

What is claimed is:

1. A substrate structure, comprising:
a substrate, comprising a dielectric layer, a plurality of pads, a patterned solder mask, a first through hole, a first surface, and a second surface opposite to the first surface, the plurality of pads being respectively disposed on two opposite surfaces of the dielectric layer, the patterned solder mask covering the two opposite surfaces and exposing the plurality of pads, wherein the first through hole penetrates the substrate for connecting the first surface and the second surface and the first through hole penetrates the dielectric layer and the patterned solder mask; and
a carrier, comprising a second through hole, a release layer, an insulating paste layer, and a metal layer, wherein the insulating paste layer is disposed between the release layer and the metal layer, the carrier is attached to the second surface by attaching the release layer to the second surface and contacting the release layer with the patterned solder mask, the second through hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole, and a smallest diameter of the second through hole is greater than a largest diameter of the first through hole.

2. The substrate structure as claimed in claim 1 , wherein a material of the release layer comprises polyethylene terephthalate (PET) or polyimide (PI) film.

3. The substrate structure as claimed in claim 1 , wherein a material of the insulating paste layer comprises prepreg (PP).

4. The substrate structure as claimed in claim 1 , wherein the metal layer comprises a copper foil layer.

5. The substrate structure as claimed in claim 1 , wherein the substrate is a single-layer circuit board.

6. The substrate structure as claimed in claim 1 , wherein the substrate is a multi-layer circuit board.

7. The substrate structure as claimed in claim 1 , wherein the substrate further comprises a plurality of vias, each of the vias connecting the corresponding pads disposed on the two opposite surfaces.

8. The substrate structure as claimed in claim 1 , further comprising:
a surface finishing layer, covering the plurality of pads.

9. A manufacturing method of a substrate structure, comprising:
providing a substrate comprising a dielectric layer, a plurality of pads, a patterned solder mask, a first surface and a second surface opposite to the first surface, the plurality of pads being respectively disposed on two opposite surfaces of the dielectric layer, the patterned solder mask covering the two opposite surfaces and exposing the plurality of pads;
forming a first through hole on the substrate, wherein the first through hole penetrates the substrate for connecting the first surface and the second surface and the first through hole penetrates the dielectric layer and the patterned solder mask;
providing a carrier comprising a release layer, an insulating paste layer, and a metal layer, wherein the insulating paste layer is disposed between the release layer and the metal layer;
forming a second through hole on the carrier, wherein the second through hole penetrates the carrier, and a smallest diameter of the second through hole is greater than a largest diameter of the first through hole; and
laminating the substrate on the release layer of the carrier, so that the release layer contacts the patterned solder mask, wherein a position of the second through hole corresponds to a position of the first through hole for exposing the first through hole.

10. The manufacturing method of the substrate structure as claimed in claim 9 , wherein the method of forming the first through hole and the second through hole comprises mechanical drilling.

11. The manufacturing method of the substrate structure as claimed in claim 9 , wherein a material of the release layer comprises polyethylene terephthalate (PET) or polyimide (PI) film.

12. The manufacturing method of the substrate structure as claimed in claim 9 , wherein a material of the insulating paste layer comprises prepreg.

13. The manufacturing method of the substrate structure as claimed in claim 9 , wherein the metal layer comprises a copper foil layer.

14. The manufacturing method of the substrate structure as claimed in claim 9 , wherein the method of providing the carrier further comprises:
forming the carrier by laminating the release layer, the insulating paste layer, and the metal layer.

15. The substrate structure as claimed in claim 1 , wherein the first though hole is adjacent to the pads.

16. The manufacturing method of the substrate structure as claimed in claim 9 , wherein the first through hole is adjacent to the pads.

Assignees

• Wang chao-min
• Subtron Technology Co Ltd

Inventors

• Wang chao-min

Classifications

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/635

  Through-vias · CPC title