Staggered parity

Patent metadata

Field	Value
Publication number	US-9537608-B2
Application number	US-201414564195-A
Country	US
Kind code	B2
Filing date	Dec 9, 2014
Priority date	Dec 9, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

In a Forward Error Correction (FEC) technique, parity vectors are computed such that: each parity vector spans a set of frames; a subset of bits of each frame is associated with parity bits in each parity vector; and a location of parity bits associated with one frame in one parity vector is different from that of parity bits associated with the frame in another parity vector. Values of decoded bits of a first frame are deduced from known parity bits of a first parity vector having an effective length of one frame. For parity vectors having, an effective length greater than one frame, a Log Likelihood Ratio of each unknown parity bit associated with the first frame is updated based on known and unknown parity bits of each parity vector. The first frame is decoded using the deduced bit values and the updated LLR values.

First claim

We claim:

1. A method of forward error correction (FEC), the method comprising a FEC encoder:
processing a data signal to generate a sequence of FEC frames; and
computing a plurality of parity vectors such that
each parity vector spans a plurality of the FEC frames,
a subset of N (where N is an integer, N>0) bits of a FEC frame is allocated to each one of at least two parity vectors, and
a respective location of the subset of N bits from a given FEC frame within one parity vector is different than the respective location of the subset of N bits from the FEC frame within another parity vector, such that the plurality of parity vectors are staggered with respect to a sequence in which the FEC frames are processed.

2. The method as claimed in claim 1 , wherein a respective different subset of N bits of a FEC frame is allocated to each one of at least two parity vectors.

3. The method as claimed in claim 1 , wherein N is less than the Hamming distance of at least one of the plurality of parity vectors.

4. The method as claimed in claim 1 , wherein at least one of the plurality of parity vectors is computed using an encoding scheme that is different than the encoding scheme used to compute another one of the plurality of parity vectors.

5. The method as claimed in claim 1 , wherein at least one of the plurality of parity vectors is computed using a binary Single Parity Check (SPC) encoding scheme.

6. The method as claimed in claim 5 , wherein the respective subset of N bits comprises a subset of rows or columns of a rectangular product FEC frame.

7. The method as claimed in claim 6 , wherein the respective subset of rows or columns are dis-contiguous.

8. The method as claimed in claim 7 , wherein the respective subset of rows or columns associated with a first parity vector are interleaved with the respective subset of rows or columns associated with at least one other parity vector.

9. The method as claimed in claim 6 , wherein a given parity vector is associated with a respective different subset of rows or columns in each of the FEC frames.

10. The method as claimed in claim 1 , wherein at least one of the plurality of parity vectors is computed using a Low Density Parity Check (LDPC) encoding scheme.

11. The method as claimed in claim 10 , wherein the respective subset of N bits are distributed across the FEC frame.

12. The method as claimed in claim 1 , further comprising a FEC decoder:
receiving a plurality of the FEC frames and parity vectors;
processing bits of a first parity vector and updating an estimate of at least one bit in a first FEC frame based on the processing result; and
decoding the first FEC frame using the updated estimate.

13. The method as claimed in claim 12 wherein updating the estimate of at least one bit comprises computing a respective Log Likelihood Ratio of the at least one bit.

14. The method as claimed in claim 13 , wherein updating the estimate of at least one bit in the first FEC frame comprises computing the sum of an LLR of the at least one bit and the processing result.

15. The method as claimed in claim 12 , wherein processing bits of a first parity vector comprises:
deducing values of parity bits of the first parity vector corresponding to a subset of bits of a first FEC frame that has been successfully decoded; and
calculating a local Log Likelihood Ratio (LLR) of parity bits of the first parity vector corresponding to a subset of bits of a second FEC frame that has not been successfully decoded.

16. The method as claimed in claim 12 , wherein the FEC frames residing in the FEC decoder exchange their respective locally calculated LLR information through one or more parity vector decoders.

17. The method as claimed in claim 16 , wherein the parity vector decoders include bits from at least one of the FEC frames which is in a decoding stage of the FEC decoder.

18. A Forward Error Correction (FEC) encoder comprising:
a processor configured to process an input data signal to generate a sequence of FEC frames; and
a parity calculator configured to compute a plurality of parity vectors such that
each parity vector spans a plurality of the FEC frames,
a subset of N (where N is an integer, N>0) bits of a FEC frame is allocated to each one of at least two parity vectors, and
a respective location of the subset of N bits from a given FEC frame within one parity vector is different than the respective location of the subset of N bits from the FEC frame within another parity vector, such that the plurality of parity vectors are staggered with respect to a sequence in which the FEC frames are processed.

19. The Forward Error Correction encoder as claimed in claim 18 , wherein at least one of the plurality of parity vectors is computed using either one of binary Single Parity Check (SPC) encoding scheme and a Low Density Parity Check (LDPC) encoding scheme.

20. A Forward Error Correction (FEC) decoder comprising:
a buffer configured to receive a plurality of FEC frames; and
a processor configured to
process bits of a first parity vector and update an estimate of at least one bit in a first FEC frame based on the processing result and
decode the first FEC frame using the updated estimate,

wherein the processor is configured to estimate of at least one bit in a first FEC frame by:
deducing a value of decoded data bits of a first FEC frame associated with a first parity vector having an effective length of one FEC frame, based on known values of parity bits of the first parity vector;
for each parity vector having an effective length corresponding to more than one FEC frame, updating a Log Likelihood Ratio (LLR) of each unknown parity bit associated with the first FEC frame based on known and unknown parity bit values of each parity vector.

Assignees

• Oveis Gharan Shahab
• Harley James
• Roberts Kim B
• Ciena Corp

Inventors

• Oveis Gharan Shahab
• Harley James
• Roberts Kim B

Classifications

• H03M13/152 Primary

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/2915

  with an error detection code in one dimension · CPC title

• H03M13/2963

  Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes · CPC title

• H03M13/2921

  wherein error correction coding involves a diagonal direction · CPC title

• H03M13/2945

  using at least three error correction codes (H03M13/2957 takes precedence) · CPC title