Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture

Patent metadata

Field	Value
Publication number	US-9537503-B2
Application number	US-201615151042-A
Country	US
Kind code	B2
Filing date	May 10, 2016
Priority date	Jul 18, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.

First claim

What is claimed is:

1. A system, comprising:
a meta-stability detector that comprises:
a timing control circuit that is operable to measure comparison time for each conversion cycle in an analog-to-digital convertor (ADC);
a plurality of signal adjustment circuits, wherein each one of the plurality of signal adjustment circuits is operable to apply a logical operation to one or more input signals to the one of the plurality of signal adjustment circuits to provide a corresponding output signal; and
a plurality of signal state circuits, wherein each one of the plurality of signal state circuits is operable to:
store state information relating to one or more input signals to the one of the plurality of signal state circuits, for at least one processing cycle; and
provide an output signal based on prior stored information;

wherein:
the plurality of signal state circuits, the plurality of signal adjustment circuits, and the timing control circuit are arranged to generate one or more control signals for controlling at least some of operations or components in the ADC, during analog-to-digital conversions, based on one or more input signals generated or used within the ADC during analog-to-digital conversions.

2. The system of claim 1 , wherein the one or more control signals are configured for controlling setting of at least a portion of an output of the ADC.

3. The system of claim 2 , wherein the setting comprises selecting between an output of a normal processing path in the ADC and an output of a code generator circuit that provides particular output when searches fail, and wherein the one or more control signals control the selecting.

4. The system of claim 3 , wherein the selecting is done on per-bit basis, to enable setting only a sequence of bits, corresponding to a portion of an overall N-bit output, based on the output of the generator circuit, and wherein the one or more control signals are configured to control the selecting on per-bit basis.

5. The system of claim 1 , wherein the one or more control signals are configured for controlling code generation in the ADC to provide particular values.

6. The system of claim 1 , wherein the plurality of signal state circuits comprise one or more D flip-flop circuits.

7. The system of claim 6 , wherein the one or more D flip-flop circuits comprise a first D flip-flop circuit that:
has its D-input set to logic zero;
is clocked based on a comparison clocking signal used in the ADC; and
is set based on a global clocking signal and a completion indication signal in the ADC.

8. The system of claim 7 , wherein an output of the first D flip-flop circuit is input into the timing control circuit.

9. The system of claim 7 , wherein the one or more D flip-flop circuits comprise a second D flip-flop circuit that:
has its D-input set to a completion indication signal in the ADC;
is clocked based on output of the timing control circuit; and
is set based on a global clocking signal in the ADC.

10. The system of claim 9 , wherein the one or more D flip-flop circuits comprise a third D flip-flop circuit that:
has its D-input set to per-bit clocking signals in the ADC;
is clocked based on output of the second D flip-flop circuit; and
is set based on a global clocking signal in the ADC.

11. The system of claim 10 , wherein the one or more control signals correspond to an output of the third D flip-flop circuit.

12. The system of claim 1 , wherein the plurality of signal adjustment circuits comprise one or more inventor circuits.

13. The system of claim 1 , wherein the plurality of signal adjustment circuits comprise one or more XOR gate circuits.

Assignees

• Maxlinear Inc

Inventors

• Chen Xuefeng
• Chan Kok Lim
• Fogleman Eric
• Ye Sheng

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/0682 Primary

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title