Pulse-width modulation control of paralleled inverters

Patent metadata

Field	Value
Publication number	US-9537427-B2
Application number	US-201414291940-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A system includes a paralleled inverter circuit and a controller. The paralleled inverter circuit includes a first inverter and a second inverter. The controller is configured to control a first plurality of switches of the first inverter and a second plurality of switches of the second inverter based upon a control vector. The controller controls the paralleled inverter circuit using a first unit vector for a first time period and controls the paralleled inverter circuit using a second unit vector for a second time period. The first unit vector and the second unit vector are selected based upon the control vector, and the first time period and the second time period are determined based upon the control vector.

First claim

The invention claimed is:

1. A system comprising:
a paralleled inverter circuit that includes a first inverter and a second inverter; and
a controller configured to control a first plurality of switches of the first inverter and a second plurality of switches of the second inverter based upon a control vector;
wherein the controller controls the paralleled inverter circuit using a first unit vector for a first time period, controls the paralleled inverter circuit using a second unit vector for a second time period, and controls the paralleled inverter circuit using a zero unit vector for a third time period, and wherein the sum of the first time period, the second time period and the third time period equals a switching period and wherein the controller comprises:
a signal calculator configured to determine the first time period, the second time period, and the third time period based upon the control vector, wherein the signal calculator generates a plurality of comparator signals; and
a pulse divider, wherein the plurality of comparator signals includes a first set of comparator signals and a second set of comparator signals, and wherein the pulse divider selects the first set of comparator signals during a first half of the switching period and selects the second set of comparator signals during a second half of the switching period; and

wherein the first unit vector and the second unit vector are selected based upon the control vector, and the first time period and the second time period are determined based upon the control vector.

2. The system of claim 1 , wherein each of the first plurality of switches and each of the second plurality of switches change state no more than two times per switching period.

3. The system of claim 1 , wherein the controller further comprises first and second pulse-width modulation calculators, and wherein the first pulse-width modulation calculator generators a first set control signals for the first plurality of switches based upon comparison of the plurality of comparator signals and a first triangle-wave carrier signal, and wherein the second pulse-width modulation calculator generates a second set of control signals for the second plurality of switches based upon comparison of the comparator signals and a second triangle-wave carrier signal.

4. The system of claim 1 , wherein the first inverter provides a first three-phase output and the second inverter provides a second three-phase output, and wherein the first three-phase output and the second-three phase output are connected by a plurality of coupling inductors.

5. The system of claim 1 , wherein a three-phase output of the plurality of coupling inductors is provided to drive an alternating current load.

6. The system of claim 4 , wherein a plurality of capacitors are connected between each of the three-phase output of the plurality of coupling inductors to filter differential-mode noise.

7. A method of controlling a paralleled inverter circuit for a switching period, wherein the paralleled inverter circuit that includes a first inverter and a second inverter is controlled based upon a control vector indicative of a desired output of the paralleled inverter circuit, the method comprising:
selecting a first unit vector based upon the control vector;
selecting a second unit vector based upon the control vector;
determining, using a controller, a first time period and a second time period based upon the control vector;
controlling, using the controller, the paralleled inverter circuit using the first unit vector for the first time period, wherein controlling, using the controller, the paralleled inverter circuit using the first unit vector for the first time period comprises:
controlling, using the controller, the first inverter using a third unit vector for a first half of the first time period;
controlling, using the controller, the second inverter using a fourth unit vector for the first half of the first time period, wherein the third unit vector and the fourth unit vector combine to form the first unit vector;
controlling, using the controller, the first inverter using the fourth unit vector for a second half of the first time period; and controlling, using the controller, the second inverter using the third unit vector for the second half of the first time period;
controlling, using the controller, the paralleled inverter circuit using the second unit vector for the second time period; and
controlling, using the controller, the paralleled inverter circuit using a zero unit vector for a third time period, wherein the sum of the first time period, the second time period, and the third time period is equal to the switching period.

8. The method of claim 7 , wherein controlling, using the controller, the paralleled inverter circuit using the second unit vector for the second time period comprises:
controlling, using the controller, the first inverter using a fifth unit vector for a first half of the second time period;
controlling, using the controller, the second inverter using a sixth unit vector for the first half of the second time period, wherein the fifth unit vector and the sixth unit vector combine to form the second unit vector;
controlling, using the controller, the first inverter using the sixth unit vector for a second half of the second time period; and
controlling, using the controller, the second inverter using the fifth unit vector for the second half of the second time period.

9. The method of claim 8 , wherein controlling, using the controller, the paralleled inverter circuit using a zero unit vector for a third time period comprises:
controlling, using the controller, the first inverter using a first zero unit vector for a first half of the third time period;
controlling, using the controller, the second inverter using a second zero unit vector for the first half of the third time period;
controlling, using the controller, the first inverter using the second zero unit vector for a second half of the third time period; and
controlling, using the controller, the second inverter using the first zero unit vector for the second half of the second time period.

10. The method of claim 7 , further comprising:
filtering, using a plurality of coupling inductors, each phase of a three-phase output of the paralleled inverter circuit; and
providing the three-phase output of the paralleled inverter circuit to drive an alternating current load.

Assignees

• Hamilton Sundstrand Corp

Inventors

• Jiang Dong

Classifications

• H02M7/5395 Primary

  by pulse-width modulation · CPC title

• H02M7/493 Primary

  the static converters being arranged for operation in parallel · CPC title