Charge injection and drain-based electrical overstress (EOS) protection apparatus and method

Patent metadata

Field	Value
Publication number	US-9537302-B2
Application number	US-201514811636-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Nov 3, 2011
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.

First claim

What is claimed is:

1. An electrical overstress (EOS) protection circuit, comprising:
a detection circuit to:
receive a first signal of a differential communication link via a first pad;
receive a second signal of the differential communication link via a second pad; and
detect an undershoot condition or an overshoot condition in the differential communication link based on a transition in the first signal or the second signal; and

a charge injection and drain circuit coupled to the detection circuit, the charge injection and drain circuit to inject charge in the first pad or the second pad in response to detection of the undershoot condition, and to drain charge from the first pad or the second pad in response to detection of the overshoot condition.

2. The EOS protection circuit of claim 1 , wherein for the undershoot condition, the charge injection and drain circuit is to inject the charge into both the first pad and the second pad.

3. The EOS protection circuit of claim 1 , wherein for the overshoot condition:
the charge injection and drain circuit is to inject charge into the first pad; and
the charge injection and drain circuit is to drain charge from the second pad.

4. The EOS protection circuit of claim 1 , wherein the first and second signals include differentially varying signals of a Universal Serial Bus (USB) protocol.

5. The EOS protection circuit of claim 1 , wherein the transition is a transition in the second signal, and wherein the detection circuit is to detect the undershoot condition or the overshoot condition in response to transition in the second signal from a first level to a second level while the first signal maintains a current level.

6. The EOS protection circuit of claim 1 ,
wherein the charge injection and drain circuit includes first and second legs configured to inject or drain charge; and
wherein the EOS protection circuit further includes a finite state machine (FSM) coupled to the charge injection and drain circuit, and configured to control timing of injection of charge by the first leg and drain of charge by the second leg in response to the overshoot.

7. The EOS protection circuit of claim 6 , wherein the charge injection and drain circuit includes:
the first and second legs;
an edge detection circuit configured to detect a transition of the second signal from a first voltage level to a second voltage level;
a logic circuit coupled to the edge detection circuit and configured to generate a window to inject or drain charge in response to the transition detected by the edge detection circuit;
a resistor-capacitor (RC)-based circuit coupled to the logic circuit and configured to control an amount and duration of charge to be injected or drained; and
a peak current limiter coupled to the first and second legs and configured to control a peak amount of charge injected or drained by the first and second legs.

8. The EOS protection circuit of claim 6 , wherein the FSM includes a Mealy-type FSM.

9. The EOS protection circuit of claim 6 , wherein the FSM includes:
a detection block to detect a condition in which the second signal transitions to a different level, while the first signal maintains a current level;
a counter coupled to the detection block and configured to count cycles in which the condition is maintained, wherein the counter includes a filter to eliminate the condition if the counted cycles are less than a threshold amount of cycles; and
a state machine unit coupled to the counter and configured to generate a signal to enable the charge injection and drain circuit, in response to the counted cycles being equal to or greater than the threshold amount of cycles.

10. The EOS protection circuit of claim 1 , wherein the EOS protection circuit is configured to generate a window to inject or drain charge, and wherein a start of the window is based on at least one logical operation performed on signals derived from the first and second signals.

11. A circuit, comprising:
means for injecting charge, by an electrical overstress (EOS) protection circuit, in response to an undershoot condition associated with first and second signals; and
means for draining charge, by the EOS protection circuit, in response to an overshoot condition associated with the second signal.

12. The circuit of claim 11 , further comprising means for, in response to the overshoot condition associated with the second signal, injecting charge, by the EOS protection circuit, in response to another undershoot condition associated with the first signal.

13. The circuit of claim 11 , wherein the means for injecting charge includes means for injecting charge into first and second pads that respectively receive the first and second signals, and wherein the means for draining charge includes draining charge from the second pad that receives the second signal.

14. The circuit of claim 11 , further comprising means for controlling a duration and amount of the draining of the charge using a finite state machine.

15. The circuit of claim 11 , further comprising means for using logical operations on signals derived from the first and second signals to determine a start of a window to inject or drain charge.

16. A system, comprising:
a processor;
a receiver circuit coupled to the processor, the receiver circuit to receive a first signal via a first pad and second signal via a second pad, wherein the first and second signals are associated with a differential communication link; and
an electrical overstress (EOS) protection circuit coupled to the receiver circuit, the EOS circuit to:
detect an undershoot condition or an overshoot condition in the differential communication link; and
inject charge into the first pad or second pad in response to the undershoot condition in the differential communication link, and drain charge from the first pad or second pad in response to the overshoot condition in the differential communication link.

17. The system of claim 16 , wherein the undershoot condition corresponds to transition of the second signal from a high level to a low level while the first signal remains at the low level, and wherein the overshoot condition corresponds to a transition of the second signal from the low level to the high level while the first signal remains at the low level.

18. The system of claim 16 , wherein the EOS protection circuit is configured to inject or drain charge to enable at least one device coupled to the differential communication link to obtain a charge profile in response to the undershoot or overshoot condition.

19. The system of claim 16 , further comprising a memory and a display coupled to the processor.

Assignees

• Intel Corp

Inventors

• Shinde Suhas Vishwasrao

Classifications

• H02H9/02 Primary

  responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)} · CPC title

• H03K19/00361 Primary

  in field effect transistor circuits · CPC title

• H02H9/00

  Emergency protective circuit arrangements for limiting excess current or voltage without disconnection · CPC title