Source/drain formation and structure

Patent metadata

Field	Value
Publication number	US-9537004-B2
Application number	US-201113114910-A
Country	US
Kind code	B2
Filing date	May 24, 2011
Priority date	May 24, 2011
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a gate stack over a channel region of a substrate;
forming a first layer adjacent to the channel region;
forming a second layer adjacent to the first layer, wherein the first layer has a higher diffusibility than the second layer and wherein the first layer has a lower concentration of a dopant than the second layer, wherein forming the first layer is performed at a higher pressure than the second layer, wherein the first layer is formed at least in part in an environment having a pressure between about 200 torr and about 1 atmospheres, and wherein the second layer is formed at least in part in an environment having a pressure between about 5 torr and about 300 torr, wherein the second layer comprises a second dopant that is different from the first dopant, wherein the first dopant has a first concentration within interstitial locations of the first layer and the second dopant has a second concentration within interstitial locations of the second layer less than the first concentration; and
performing an annealing process, wherein the annealing process diffuses a first material from the first layer into the channel region.

2. The method of claim 1 , further comprising forming a recess in the substrate adjacent to the channel region, wherein the forming the first layer forms the first layer along a bottom of the recess.

3. The method of claim 2 , wherein the forming the second layer comprises forming the second layer over the first layer, the second layer filling the recess.

4. The method of claim 3 , wherein the forming the second layer comprises forming the second layer such that the second layer extends above the substrate.

5. The method of claim 1 , wherein the first layer and the second layer comprise the same atomic compound.

6. The method of claim 1 , further comprising forming a recess in the substrate adjacent to the channel region, wherein the forming the second layer comprises forming the second layer along a bottom of the recess.

7. The method of claim 6 , wherein the forming the first layer forms the first layer over the second layer and adjacent to the channel region.

8. The method of claim 1 , wherein the forming the first layer is performed at least in part in an environment having a temperature between about 550° C. and about 750° C.

9. A method of manufacturing a semiconductor device, the method comprising:
forming a gate stack over a substrate;
removing a portion of the substrate to form a recess in the substrate adjacent to the gate stack, wherein the removing the portion of the substrate forms a sidewall;
forming a first layer within the recess, the first layer having a first diffusibility, wherein the first layer comprises a first dopant, wherein the forming the first layer is performed at least in part at a pressure between about 200 torr and about 1 atmospheres, and wherein the first layer is in physical contact with the sidewall along the entire length of the recess;
forming a second layer within the recess, wherein the second layer has a second diffusibility lower than the first diffusibility, wherein the forming the second layer is performed at least in part in an environment having a pressure between about 5 torr and about 300 torr, wherein the first layer is formed at a higher pressure than the second layer, wherein the second layer comprises a second dopant that is different from the first dopant, wherein the first dopant has a first concentration within interstitial locations of the first layer and the second dopant has a second concentration within interstitial locations of the second layer less than the first concentration, and wherein the first layer and the second layer jointly fill the recess; and
annealing the first layer such that dopants within the first layer diffuse into the substrate beneath the gate stack.

10. The method of claim 9 , wherein the forming the first layer is performed before the forming the second layer.

11. The method of claim 9 , wherein the forming the second layer is performed before the forming the first layer.

12. The method of claim 9 , wherein the forming the first layer further comprises forming a third layer, the third layer comprising silicon and phosphorous.

13. The method of claim 12 , wherein the forming the second layer further comprises forming a fourth layer, the fourth layer comprising silicon and phosphorous.

14. A method of manufacturing a semiconductor device, the method comprising:
depositing a gate stack over a substrate;
removing a portion of the substrate to form a recess;
depositing a first layer into the recess, the first layer comprising a first dopant with a first diffusibility into the substrate, wherein the depositing the first layer is performed at least in part at a pressure between about 200 torr and about 1 atmospheres;
depositing a second layer into the recess, the second layer comprising a second dopant with a second diffusibility into the substrate, wherein the second diffusibility is less than the first diffusibility, wherein the first dopant has a first concentration within interstitial locations of the first layer and the second dopant has a second concentration within interstitial locations of the second layer less than the first concentration, and wherein the depositing the second layer is performed at least in part in an environment having a pressure between about 5 torr and about 300 torr; and
annealing the first layer and the second layer to diffuse the first dopant into the substrate.

15. The method of claim 14 , wherein the depositing the first layer is performed prior to the depositing the second layer.

16. The method of claim 14 , wherein the depositing the second layer is performed prior to the depositing the first layer.

17. The method of claim 14 , wherein the depositing the first layer further comprises depositing a third layer, the third layer comprising silicon and phosphorous.

18. The method of claim 14 , wherein the depositing the second layer further comprises depositing a fourth layer, the fourth layer comprising silicon and phosphorous.

Assignees

• Wu Chii-Ming
• Su Chien-Chang
• Lin Hsien-Hsin
• Pai Yi-Fang
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chii-Ming
• Su Chien-Chang
• Lin Hsien-Hsin
• Pai Yi-Fang

Classifications

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D30/608 Primary

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title