Reduction of degradation due to hot carrier injection

Patent metadata

Field	Value
Publication number	US-9537001-B2
Application number	US-201514752373-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Jul 30, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.

First claim

What is claimed is:

1. A high-voltage metal-oxide-semiconductor (HVMOS) device comprising:
a first gate dielectric layer disposed on a channel region of the HVMOS device; and
a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device, the drift region being disposed laterally adjacent to the channel region, the first gate dielectric having a portion disposed under at least a portion of the second gate dielectric,
the second gate dielectric layer having a thickness that is greater than a thickness of the first gate dielectric layer.

2. The HVMOS device of claim 1 , further comprising:
a gate electrode disposed on the first gate dielectric layer and the second gate dielectric layer.

3. The HVMOS device of claim 1 , further comprising:
a source region disposed laterally adjacent to the channel region;
a field oxide (FOX) layer, at least a portion of the FOX layer disposed laterally adjacent to the drift region; and
a drain region, at least a portion of the drain region being disposed laterally adjacent to the FOX layer.

4. The HVMOS device of claim 3 , wherein at least a portion of the second gate dielectric layer is disposed on the FOX layer.

5. The HVMOS device of claim 1 , wherein:
the first gate dielectric layer has a thickness of less than or equal to 115 angstroms; and
the second gate dielectric layer has a thickness of less than or equal to 560 angstroms.

6. The HVMOS device of claim 1 , wherein:
the channel region has a lateral width in a range of 0.1 microns (μm) to 1.0 μm; and
the drift region has a lateral width in a range of 0.2 μm to 3.0 μm.

7. The HVMOS device of claim 1 , wherein a vertical edge of the second gate dielectric layer is laterally spaced from the channel region by a distance in a range of 0 microns (μm) to 1.0 μm.

8. A high-voltage metal-oxide-semiconductor (HVMOS) device comprising:
a first gate dielectric layer disposed on a channel region of the HVMOS device;
a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device, the drift region being disposed laterally adjacent to the channel region; and
a third gate dielectric layer disposed on at least a portion of the second gate dielectric layer,
the second gate dielectric layer having a thickness that is greater than a thickness of the first gate dielectric layer, the third gate dielectric layer having a thickness that is greater than the thickness of the second gate dielectric layer.

9. The HVMOS device of claim 8 , further comprising:
a gate electrode disposed on the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer.

10. The HVMOS device of claim 8 , further comprising:
a source region disposed laterally adjacent to the channel region;
a field oxide (FOX) layer, at least a portion of the FOX layer being disposed laterally adjacent to the drift region; and
a drain region, at least a portion of the drain region being disposed laterally adjacent to the FOX layer.

11. The HVMOS device of claim 10 , wherein at least a portion of the second gate dielectric layer and at least a portion of the third gate dielectric layer are disposed on the FOX layer.

12. The HVMOS device of claim 8 , wherein:
the first gate dielectric layer has a thickness of less than or equal to 115 angstroms;
the second gate dielectric layer has a thickness of less than or equal to 600 angstroms; and
the third dielectric layer has a thickness of less than or equal to 2000 angstroms.

13. The HVMOS device of claim 8 , wherein:
the channel region has a lateral width in a range of 0.1 microns (μm) to 1.0 μm; and
the drift region has a lateral width in a range of 0.2 μm to 3.0 μm.

14. The HVMOS device of claim 8 , wherein:
a vertical edge of the second gate dielectric layer is laterally spaced from the channel region by a distance in a range of 0 microns (μm) to 1.0 μm; and
a vertical edge of the third gate dielectric layer is laterally spaced from the vertical edge of the second gate dielectric by a distance in a range of 0 μm to 1.0 μm.

15. The HVMOS device of claim 8 , wherein the first gate dielectric layer is further disposed under at least a portion of the second gate dielectric.

16. The HVMOS device of claim 8 , wherein a ratio of a combined thickness of the second gate dielectric layer and the third gate dielectric layer to the thickness of the first gate dielectric layer is approximately 20:1.

17. A method comprising:
forming a first gate dielectric layer disposed on at least a portion of a drift region of a high-voltage metal-oxide-semiconductor (HVMOS) device, the drift region being disposed laterally adjacent to a channel region of the HVMOS device; and
forming a second gate dielectric layer disposed on the channel region, the forming the second gate dielectric including forming the second gate dielectric under at least a portion of the first gate dielectric,
the first gate dielectric layer having a thickness that is greater than a thickness of the second gate dielectric layer.

18. The method of claim 17 , wherein the method, prior to forming the second dielectric layer, further comprises:
forming a third gate dielectric layer disposed on at least a portion of the first gate dielectric layer,
the third gate dielectric layer having a thickness that is greater than the thickness of the first gate dielectric layer.

19. The method of claim 17 , wherein a thickness of the second gate dielectric under the first gate dielectric is less than a thickness of the second gate dielectric in the channel region.

Assignees

• Fairchild Semiconductor

Inventors

• Hao Jifa
• Hahn Daniel

Classifications

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/109

  Reduced surface field [RESURF] PN junction structures · CPC title