Semiconductor structure including a ferroelectric transistor and method for the formation thereof

Patent metadata

Field	Value
Publication number	US-9536992-B2
Application number	US-201615041581-A
Country	US
Kind code	B2
Filing date	Feb 11, 2016
Priority date	Jul 29, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

First claim

What is claimed:

1. A method, comprising:
providing a semiconductor structure comprising a first transistor region, a second transistor region, and a silicon dioxide layer on said first transistor region and said second transistor region;
depositing a layer of a high-k dielectric material on said silicon dioxide layer;
forming a layer of a first metal over said second transistor region, wherein said layer of said first metal does not cover said first transistor region;
after the formation of said layer of said first metal, depositing a layer of a second metal over said first transistor region and said second transistor region;
performing a first annealing process, said first annealing process initiating a scavenging reaction between said second metal and silicon dioxide from a portion of said silicon dioxide layer on said first transistor region; and
after said first annealing process, forming a ferroelectric transistor dielectric over said first transistor region.

2. The method of claim 1 , further comprising forming a layer of a third metal over said ferroelectric transistor dielectric.

3. The method of claim 2 , wherein forming said ferroelectric transistor dielectric and said layer of said third metal comprises:
forming said ferroelectric transistor dielectric over said first and second transistor regions;
forming said layer of said third metal over said ferroelectric transistor dielectric; and
selectively removing said ferroelectric transistor dielectric and said layer of said third metal from said second transistor region using said layer of said second metal as an etch stop layer.

4. The method of claim 3 , further comprising performing a second annealing process so as to re-crystallize said ferroelectric transistor dielectric to provide a crystal structure of said ferroelectric transistor dielectric having ferroelectric properties prior to selectively removing said ferroelectric transistor dielectric and said layer of said third metal from said second transistor region.

5. The method of claim 2 , further comprising:
forming a first gate electrode over said first transistor region; and
forming a second gate electrode over said second transistor region.

6. The method of claim 2 , further comprising performing a second annealing process so as to re-crystallize said ferroelectric transistor dielectric to provide a crystal structure of said ferroelectric transistor dielectric having ferroelectric properties.

7. The method of claim 2 , wherein said third metal comprises titanium nitride.

8. The method of claim 1 , wherein said layer of said high-k dielectric material comprises hafnium dioxide.

9. The method of claim 1 , wherein said second metal comprises at least one of hafnium, titanium, or a titanium nitride alloy.

10. A method, comprising:
forming a silicon dioxide layer on a first transistor region and a second transistor region;
forming a layer of a high-k dielectric material on said silicon dioxide layer;
forming a layer of a first metal over said second transistor region, wherein said layer of said first metal does not cover said first transistor region;
after the formation of said layer of said first metal, depositing a layer of a second metal over said first transistor region and said second transistor region;
performing a first annealing process, said first annealing process initiating a scavenging reaction between said second metal and silicon dioxide from a portion of said silicon dioxide layer on said first transistor region;
after said first annealing process, forming a ferroelectric transistor dielectric over said first and second transistor regions;
forming a layer of a third metal over said ferroelectric transistor dielectric; and
performing a second annealing process so as to re-crystallize said ferroelectric transistor dielectric to provide a crystal structure of said ferroelectric transistor dielectric having ferroelectric properties.

11. The method of claim 10 , further comprising selectively removing said ferroelectric transistor dielectric and said layer of said third metal from said second transistor region using said layer of said second metal as an etch stop layer.

12. The method of claim 11 , wherein performing said second annealing process comprises performing said second annealing process prior to selectively removing said ferroelectric transistor dielectric and said layer of said third metal from said second transistor region.

13. The method of claim 10 , further comprising:
forming a first gate electrode over said first transistor region; and
forming a second gate electrode over said second transistor region.

14. The method of claim 10 , wherein said third metal comprises titanium nitride.

15. The method of claim 10 , wherein said layer of said high-k dielectric material comprises hafnium dioxide.

16. The method of claim 10 , wherein said second metal comprises at least one of hafnium, titanium, or a titanium nitride alloy.

Assignees

• Globalfoundries Inc

Inventors

• Van Bentum Ralf
• Yun Jongsin
• Seo Seunghwan
• Schmid Joerg

Classifications

• H10D64/01332

  Making the insulator · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title