Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
US9536902B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9536902-B2 |
| Application number | US-201414401105-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 10, 2014 |
| Priority date | Sep 12, 2014 |
| Publication date | Jan 3, 2017 |
| Grant date | Jan 3, 2017 |
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A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a thin film transistor array substrate, comprising: A) forming a first metal layer in a pixel electrode layout area and a data electrode layout area using a first photo mask; B) depositing a first dielectric layer; C) forming a second metal layer on the first dielectric layer using a second photo mask; D) depositing a second dielectric layer; E) forming a via hole in a pixel electrode layout area of a second dielectric layer using a third photo mask; F) forming a transparent pixel electrode layer on the pixel electrode layout area of the second dielectric layer using a fourth photo mask, wherein the transparent pixel electrode layer is connected to the pixel electrode layout area of second metal layer via the via hole; wherein the method further comprises a step of depositing a photoresist layer on the first dielectric layer prior to execute the step C). 2. The method of claim 1 , wherein the photoresist layer is a red photoresist layer, a green photoresist layer or a blue photoresist layer. 3. A liquid crystal display, comprising a thin film transistor array substrate, a second substrate opposite to the thin film transistor array substrate, and a liquid crystal layer interposed between the thin film transistor array substrate and the second substrate; the thin film transistor array substrate, comprising: a pixel electrode layout area and a data electrode layout area; the thin film transistor array substrate further comprising a transparent pixel electrode layer formed in the pixel electrode layout area, and further comprising a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer and a second dielectric layer all formed in the pixel electrode layout are and the data electrode layout area; the first dielectric layer covering the first metal layer; the amorphous silicon layer, the second metal layer and the second dielectric being sequentially formed on the first dielectric layer and thereby the first dielectric layer being located between the first metal layer and the amorphous silicon layer; the transparent pixel electrode layer being connected to the second metal layer via a via hole formed in the pixel electrode area of the second dielectric layer; wherein the thin film transistor array substrate further comprises a photoresist layer formed between the first dielectric layer and the amorphous silicon layer and thereby the first metal layer, the first dielectric layer, the photoresist layer and the amorphous silicon layer are sequentially arranged in that order. 4. The liquid crystal display of claim 3 , wherein the photoresist layer is a red photoresist layer, a green photoresist layer or a blue photoresist layer.
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