Methods of fabricating three-dimensional semiconductor devices

Patent metadata

Field	Value
Publication number	US-9536895-B2
Application number	US-201514657849-A
Country	US
Kind code	B2
Filing date	Mar 13, 2015
Priority date	Nov 5, 2010
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

First claim

What is claimed is:

1. A method of fabricating a three-dimensional semiconductor device, the method comprising:
sequentially stacking a lower structure, an underlying layer, and an upper structure;
forming an opening penetrating the upper structure such that a portion of the underlying layer remains below the opening;
forming an insulating layer on an inner wall of the opening;
forming a recessed hole penetrating a lower region of the insulating layer and the portion of the underlying layer to form an insulating spacer in the opening, the recessed hole exposing a top surface of the lower structure; and
forming a semiconductor pattern covering the insulating spacer in the opening, the semiconductor pattern being in direct contact with the inner wall of the recessed hole; wherein a bottom surface of the insulating spacer is positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

2. The method as claimed in claim 1 , wherein forming the insulating spacer includes exposing the lower structure through an insulating layer, and forming the semiconductor pattern includes forming a semiconductor core to cover an inner sidewall of the insulating spacer and the exposed lower structure.

3. The method as claimed in claim 1 , wherein forming the lower structure includes forming a semiconductor substrate, such that the semiconductor pattern is directly connected to the semiconductor substrate.

4. The method as claimed in claim 3 , wherein forming the semiconductor substrate includes:
forming a doped region apart from the semiconductor pattern, the doped region having a different conductivity type from the semiconductor pattern; and
forming a connection region directly connected to the semiconductor pattern, the connection region having the same conductivity type as the semiconductor pattern.

5. The method as claimed in claim 1 , wherein forming the lower structure includes forming a substrate and a selection transistor interposed between the substrate and the upper structure, the selection transistor including a selection semiconductor pattern directly connected to the semiconductor pattern, and the bottom surface of the insulating spacer being positioned at a vertical level higher than the uppermost top surface of the selection semiconductor pattern.

6. The method as claimed in claim 1 , wherein forming the lower structure includes forming three-dimensionally arranged lower memory devices and a pad pattern interposed between the lower memory devices and the semiconductor pattern, the bottom surface of the insulating spacer being positioned at a vertical level higher than the uppermost top surface of the pad pattern.

7. The method as claimed in claim 1 , wherein the semiconductor pattern is in direct contact with the bottom surface of the insulating spacer.

8. The method as claimed in claim 1 , wherein a distance between the bottom surface of the insulating spacer and an uppermost surface of the lower structure is less than a thickness of one of the conductive patterns.

9. A method of fabricating a three-dimensional semiconductor device, the method comprising:
forming an upper structure on a lower structure;
forming a semiconductor pattern connected to the lower structure through the upper structure; and
forming an insulating spacer between the semiconductor pattern and the upper structure, such that a bottom surface of the insulating spacer is positioned at a vertical level substantially equivalent to or higher than an uppermost surface of the lower structure, wherein:
forming the upper structure on the lower structure includes forming a layer stack on the lower structure, the layer stack including a plurality of horizontal layers sequentially deposited on the lower structure, and
forming the insulating spacer includes:
forming an opening in the layer stack,
forming an insulating layer on an inner wall of the opening, such that the opening is spaced apart from the lower structure, and such that at least one of the horizontal layers remains between a bottom surface of the opening and the lower structure, and
forming a recessed hole penetrating a lower region of the insulating layer and the at least one horizontal layer to expose a top surface of the lower structure.

10. The method as claimed in claim 9 , further comprising:
forming the semiconductor pattern on the insulating spacer such that the semiconductor pattern is directly connected to the lower structure through the layer stack .

11. The method as claimed in claim 9 , wherein forming one of the plurality of horizontal layers includes forming a layer of aluminum oxide as an etch stop layer during formation of the opening.

12. The method as claimed in claim 9 , wherein forming the layer stack includes forming alternating first horizontal layers and second horizontal layers of the plurality of horizontal layers on the lower structure, the first horizontal layers being formed of silicon oxide, and the second horizontal layers being formed of a material having an etch selectivity with respect to the first horizontal layers.

13. The method as claimed in claim 12 , wherein forming the layer stack includes forming one of the first horizontal layers as a lowermost layer.

14. The method as claimed in claim 12 , wherein forming the layer stack includes forming one of the second horizontal layers as a lowermost layer.

15. The method as claimed in claim 12 , further comprising, after forming the semiconductor pattern:
removing the second horizontal layers to form recess regions exposing a sidewall of the insulating spacer between the first horizontal layers; and
forming conductive patterns in the recess regions.

16. The method as claimed in claim 15 , further comprising, before forming the conductive patterns, forming an intermediate pattern in the recess region, such that the intermediate pattern and the insulating spacer define a memory layer.

17. The method as claimed in claim 15 , further comprising, before forming the conductive patterns:
etching the exposed insulating spacer to expose a sidewall of the semiconductor pattern; and
forming an intermediate pattern to cover the exposed sidewall of the semiconductor pattern, such that the insulating spacer remains in regions localized between the semiconductor pattern and the first horizontal layers.

18. The method as claimed in claim 17 , wherein forming the insulating spacer includes forming a layer of at least one material having an etch selectivity with respect to the second horizontal layer.

Assignees

• Lee Changhyun
• Park Chanjin
• Son Byoungkeun
• Chang Sung-Il
• Samsung Electronics Co Ltd

Inventors

• Lee Changhyun
• Park Chanjin
• Son Byoungkeun
• Chang Sung-Il

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H01L27/11551

  Electricity · mapped topic