Hybrid FINFET/nanowire SRAM cell using selective germanium condensation

Patent metadata

Field	Value
Publication number	US-9536885-B2
Application number	US-201514672282-A
Country	US
Kind code	B2
Filing date	Mar 30, 2015
Priority date	Mar 30, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A semiconductor device including a pFET and an nFET where: (i) the gate and conductor channel of the pFET are electrically insulated from a buried oxide layer; and (ii) the conductor channel of the nFET is in the form of a fin extending upwards from, and in electrical contact with, the buried oxide layer. Also, a method of making the pFET by adding a fin structure extending from the top surface of the buried oxide layer, then condensing germanium locally into the lattice structure of the lower portion of the fin structure, and then etching away the lower portion of the fin structure so that it becomes a carrier channel suspended above, and electrically insulated from the buried oxide layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a buried oxide layer (BOX);
a first pFET (p-type field-effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate; and
a first nFET (n-type field effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate;
wherein:
the conducting channel of the first pFET device is: (i) located above the BOX, and (ii) substantially electrically insulated from the BOX; and
the conducting channel of the first nFET device is in the form of a fin extending upwards from, and in electrically conductive contact with, the BOX.

2. The semiconductor device of claim 1 wherein:
the gate of the first pFET device is in the form of suspended nanowire.

3. The semiconductor device of claim 1 wherein:
the gate of the first pFET device and the gate of a second nFET device are two different longitudinal portions of an elongated and continuous piece of material.

4. The semiconductor device of claim 1 further comprising:
a dielectric material portion located to extend in the space between: (i) the BOX, and (ii) an underside of the gate of the first pFET device and an underside of the conducting channel of the first pFET device.

5. A static random-access memory (SRAM) cell device comprising:
a buried oxide layer (BOX);
a first pFET (p-type field-effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate; and
a first nFET (n-type field effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate;
wherein:
the conducting channel of the first pFET device is: (i) located above the BOX, and (ii) substantially electrically insulated from the BOX; and
the conducting channel of the first nFET device is in the form of a fin extending upwards from, and in electrically conductive contact with, the BOX.

6. The SRAM cell device of claim 5 wherein:
the gate of the first pFET device is in the form of suspended nanowire.

7. The SRAM cell device of claim 5 wherein:
the gate of the first pFET device and the gate of the second nFET device are two different longitudinal portions of an elongated and continuous piece of material.

8. The SRAM cell device of claim 5 further comprising:
a dielectric material portion located to extend in the space between: (i) the BOX, and (ii) an underside of the gate of the first pFET device and an underside of the conducting channel of the first pFET device.

9. The SRAM cell device of claim 5 further comprising:
a second pFET (p-type field-effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate; and
a second nFET (n-type field effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate;
wherein:
the conducting channel of the second pFET device is: (i) located above the BOX, and (ii) substantially electrically insulated from the BOX; and
the conducting channel of the second nFET device is in the form of a fin extending upwards from, and in electrically conductive contact with, the BOX.

10. The SRAM cell device of claim 9 further comprising:
a third nFET (n-type field effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate; and
a fourth nFET (n-type field effect transistor) device including a source, a drain, a gate, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate;
wherein:
the conducting channel of the third nFET device is in the form of a fin extending upwards from, and in electrically conductive contact with, the BOX;
the conducting channel of the fourth nFET device is in the form of a fin extending upwards from, and in electrically conductive contact with, the BOX; and
the third and fourth nFET devices are each structured, located and/or connected to act as a pass gate.

11. The SRAM cell device of claim 10 further comprising:
a fifth nFET (n-type field effect transistor) device including a source, a drain, a gate and a conducting channel, with the semiconductor conducting channel extending from the source to the drain and being in electrically conductive contact with the gate;
wherein:
the conducting channel of the fifth nFET device is in the form of a fin extending upwards from, and in electrically conductive contact with, the BOX; and
the fifth nFET device is structured, located and/or connected to act as a read stack.

Assignees

• IBM

Inventors

• Chang Josephine B
• Chang Leland
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D86/215

  comprising FinFETs · CPC title