Semiconductor device

Patent metadata

Field	Value
Publication number	US-9536875-B2
Application number	US-201514882427-A
Country	US
Kind code	B2
Filing date	Oct 13, 2015
Priority date	Oct 4, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n − -type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n − -type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n − -type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (α) is 50% to 100%.

First claim

What is claimed is:

1. A semiconductor device comprising a first element region in which an insulated gate bipolar transistor is provided and a second element region in which a diode is provided on a semiconductor substrate that forms a first conductivity type drift region, the semiconductor device further comprising:
a plurality of trenches provided in stripe form extending in a trench longitudinal direction perpendicular to a direction in which the first element region and second element region are aligned from the first element region across the second element region in a front surface of the semiconductor substrate;
a gate insulating film provided along side walls and bottom surfaces of the trenches;
a gate electrode provided on an inner side of the gate insulating film inside the trenches;
a second conductivity type base region selectively provided in a mesa portion between neighboring trenches of the first element region;
a second conductivity type anode region selectively provided in the mesa portion between neighboring trenches of the second element region;
a first conductivity type emitter region selectively provided inside the base region;
a first electrode in contact with the base region, emitter region, and anode region;
a second conductivity type collector region provided on a back surface of the semiconductor substrate in the first element region;
a first conductivity type cathode region provided on the back surface of the semiconductor substrate in the second element region; and
a second electrode in contact with the collector region and cathode region, wherein
the anode region and drift region are repeatedly, alternately disposed in the trench longitudinal direction in a top surface of the mesa portion between neighboring trenches of the second element region.

2. The semiconductor device according to claim 1 , wherein built-in depletion layers spreading into the mesa portion from each of neighboring anode regions are linked to each other.

3. The semiconductor device according to claim 1 , wherein
the first electrode is further in contact with the drift region in the second element region, and
a proportion occupied by the anode region of a unit region formed of the anode region and the drift region in a portion sandwiched by the anode region and the anode region neighboring the anode region in the trench longitudinal direction is less than 50%.

4. The semiconductor device according to claim 3 , wherein the drift region and the first electrode form a Schottky junction.

5. A semiconductor device comprising:
an insulated gate bipolar transistor (IGBT) region;
a diode region adjacent to the IGBT region;
wherein
the diode region includes parallel trenches and a repeating pattern of an anode region alternating with a drift region on a surface between the parallel trenches, and
a unit region in the diode region is defined as an anode region and an adjacent drift region on the surface between the parallel trenches.

6. A semiconductor device according to claim 5 , wherein
a first electrode is in contact with the drift region in the diode region, and
an anode ratio, defined as a ratio of a dimension of the anode region of the unit region to a dimension of the unit region as a whole, is less than 50%.

7. The semiconductor device of claim 6 , wherein an anode region and a drift region are connected to a common emitter electrode.

8. The semiconductor device according to claim 1 , wherein
the drift region in the top surface of the mesa portion is covered by an insulator film, and
a proportion occupied by the anode region of a unit region formed of the anode region and the drift region in a portion sandwiched by the anode region and the anode region neighboring the anode region in the trench longitudinal direction is 50% or more and less than 100%.

9. The semiconductor device of claim 5 , wherein
the drift region between the surface of the parallel trenches is covered by an insulator film, and
an anode ratio, defined as a ratio of a dimension of the anode region of the unit region to a dimension of the unit region as a whole, is 50% or more and less than 100%.

10. The semiconductor device of claim 7 , wherein the drift region and the first electrode form a Schottky junction.

11. The semiconductor device of claim 9 , wherein the anode ratio is between substantially 50% and substantially 75%.

12. The semiconductor device of claim 9 , wherein the anode ratio is substantially 75%.

Assignees

• Fuji Electric Co Ltd

Inventors

• Tamura Masaki
• Yoshida Souichi
• Adachi Shinichiro

Classifications

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/83 Primary

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title